linux-kernel - RE: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk

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Message-ID: <CB4ED07B85D6BB40B8B44F6D5442E4F6572C38D7@BGSMSX101.gar.corp.intel.com>
Date:   Fri, 14 Feb 2020 06:26:42 +0000
From:   "Srivastava, Shobhit" <shobhit.srivastava@...el.com>
To:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
CC:     Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
        Rajat Jain <rajatja@...gle.com>,
        Daniel Mack <daniel@...que.org>,
        Haojian Zhuang <haojian.zhuang@...il.com>,
        Robert Jarzmik <robert.jarzmik@...e.fr>,
        "Mark Brown" <broonie@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Evan Green <evgreen@...omium.org>,
        "rajatxjain@...il.com" <rajatxjain@...il.com>,
        "evgreen@...gle.com" <evgreen@...gle.com>,
        "Muthukrishnan, Porselvan" <porselvan.muthukrishnan@...el.com>
Subject: RE: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk

> 
> On Thu, Feb 13, 2020 at 04:57:24PM +0000, Srivastava, Shobhit wrote:
> > > On 2/12/20 12:34 AM, Rajat Jain wrote:
> 
> ...
> 
> > > I wonder is it enough to have this quick toggling only or is time or
> > > actually number of clock cycles dependent? Now there is no delay
> > > between but I'm thinking if it needs certain number cycles does this
> > > still work when using low ssp_clk rates similar than in commit
> d0283eb2dbc1 ("spi:
> > > pxa2xx: Add output control for multiple Intel LPSS chip selects").
> > >
> > > I'm thinking can this be done only once after resume and may other
> > > LPSS blocks need the same? I.e. should this be done in drivers/mfd/intel-
> lpss.c?
> 
> > This behavior is seen after S0ix resume, but it is not seen after S3 resume.
> 
> I already commented in the other thread about this.
> 
> Have you checked what's going on in intel_lpss_suspend() and
> intel_lpss_resume() for your case?
Yes, I checked those functions and they look fine.
I even dumped all the relevant registers for both S3 resume & S0ix resume case.
All registers were same except the SSCR0.

> Is intel_lpss_prepare() called during S0ix exit?
Yes, it is called during S0ix entry, before the suspend callback.

> > I am thinking that it happens because we are not enabling the SSP after
> resume.
> > It is deferred until we need to send data. By enabling the SSP in resume, I
> don’t see the issue.
> > For S3, I think BIOS re-enables the SSP in resume flow.
> 
> --
> With Best Regards,
> Andy Shevchenko
>