lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Fri, 14 Feb 2020 16:45:38 +0530
From:   Rajendra Nayak <rnayak@...eaurora.org>
To:     agross@...nel.org, bjorn.andersson@...aro.org
Cc:     linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        mka@...omium.org
Subject: Re: [PATCH 1/3] arm64: dts: qcom: sc7180: Add dynamic CPU power
 coefficients



On 1/7/2020 4:15 PM, Rajendra Nayak wrote:
> Add dynamic power coefficients for Silver and Gold CPUs on
> SC7180 SoC.
> 
> Signed-off-by: Rajendra Nayak <rnayak@...eaurora.org>
> ---

Andy/Bjorn, can we pull this series in for 5.7?
Its essential to get EAS function on sc7180 devices.

>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 8011c5f..fb78bb8 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -86,6 +86,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x0>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <100>;
>   			next-level-cache = <&L2_0>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -103,6 +104,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x100>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <100>;
>   			next-level-cache = <&L2_100>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -117,6 +119,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x200>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <100>;
>   			next-level-cache = <&L2_200>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -131,6 +134,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x300>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <100>;
>   			next-level-cache = <&L2_300>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -145,6 +149,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x400>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <100>;
>   			next-level-cache = <&L2_400>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -159,6 +164,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x500>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <100>;
>   			next-level-cache = <&L2_500>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 0>;
> @@ -173,6 +179,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x600>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <405>;
>   			next-level-cache = <&L2_600>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 1>;
> @@ -187,6 +194,7 @@
>   			compatible = "arm,armv8";
>   			reg = <0x0 0x700>;
>   			enable-method = "psci";
> +			dynamic-power-coefficient = <405>;
>   			next-level-cache = <&L2_700>;
>   			#cooling-cells = <2>;
>   			qcom,freq-domain = <&cpufreq_hw 1>;
> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Powered by blists - more mailing lists