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Date:   Sat, 15 Feb 2020 10:26:09 +0100
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Sean V Kelley <sean.v.kelley@...ux.intel.com>, bhelgaas@...gle.com,
        corbet@....net, mingo@...hat.com, bp@...en8.de
Cc:     x86@...nel.org, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
        kar.hin.ong@...com, sassmann@...nic.de,
        Sean V Kelley <sean.v.kelley@...ux.intel.com>
Subject: Re: [PATCH 0/2] Add boot interrupt quirk mechanism for Xeon chipsets

Thomas Gleixner <tglx@...utronix.de> writes:

> Sean V Kelley <sean.v.kelley@...ux.intel.com> writes:
>> When IRQ lines on secondary or higher IO-APICs are masked (e.g.,
>> Real-Time threaded interrupts), many chipsets redirect IRQs on
>> this line to the legacy PCH and in turn the base IO-APIC in the
>> system. The unhandled interrupts on the base IO-APIC will be
>> identified by the Linux kernel as Spurious Interrupts and can
>> lead to disabled IRQ lines.
>>
>> Disabling this legacy PCI interrupt routing is chipset-specific and
>> varies in mechanism between chipset vendors and across generations.
>> In some cases the mechanism is exposed to BIOS but not all BIOS
>> vendors choose to pick it up. With the increasing usage of RT as it
>> marches towards mainline, additional issues have been raised with
>> more recent Xeon chipsets.
>>
>> This patchset disables the boot interrupt on these Xeon chipsets where
>> this is possible with an additional mechanism.  In addition, this
>> patchset includes documentation covering the background of this quirk.
>
> Well done! The documentation is really appreciated!
>
> Reviewed-by: Thomas Gleixner <tglx@...utronix.de>

Bjorn, this should go into stable as well IMO.

Thanks,

        tglx

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