linux-kernel - [PATCH v5 3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP.

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Message-Id: <1581792932-108032-5-git-send-email-zhouyanjie@wanyeetech.com>
Date:   Sun, 16 Feb 2020 02:55:28 +0800
From:   周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>
To:     linux-mips@...r.kernel.org
Cc:     linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, paul@...pouillou.net,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        mark.rutland@....com, ralf@...ux-mips.org, paulburton@...nel.org,
        jiaxun.yang@...goat.com, chenhc@...ote.com, allison@...utok.net,
        tglx@...utronix.de, daniel.lezcano@...aro.org,
        geert+renesas@...der.be, krzk@...nel.org, keescook@...omium.org,
        ebiederm@...ssion.com, miquel.raynal@...tlin.com,
        paul@...die.org.uk, hns@...delico.com,
        mips-creator-ci20-dev@...glegroups.com
Subject: [PATCH v5 3/7] MIPS: CI20: Modify DTS to support high resolution timer for SMP.

Modify DTS, change tcu channel from 2 to 3, channel #0 and #1 for
per core local timer, #2 for clocksource.

Tested-by: H. Nikolaus Schaller <hns@...delico.com>
Tested-by: Paul Boddie <paul@...die.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---

Notes:
    v1->v2:
    No change.
    
    v2->v3:
    No change.
    
    v3->v4:
    Rebase on top of kernel 5.6-rc1.
    
    v4->v5:
    Move [5/6] in v4 to this patch, to ensure that we can
    git-bisect without ending up with a broken kernel.

 arch/mips/boot/dts/ingenic/ci20.dts | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 37b9316..29437aa 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -455,7 +455,14 @@
 };
 
 &tcu {
-	/* 3 MHz for the system timer and clocksource */
-	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
-	assigned-clock-rates = <3000000>, <3000000>;
+	/* 3 MHz for the system timers, 750kHz for the clocksource */
+	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+					  <&tcu TCU_CLK_TIMER2>;
+	assigned-clock-rates = <3000000>, <3000000>, <750000>;
+
+	/*
+	 * Use channel #0 and #1 for the per core system timer,
+	 * and use channel #2 for the clocksource.
+	 */
+	ingenic,pwm-channels-mask = <0xF8>;
 };
-- 
2.7.4