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Date: Mon, 17 Feb 2020 14:21:29 +0530 From: Anand Moon <linux.amoon@...il.com> To: Jerome Brunet <jbrunet@...libre.com> Cc: Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Neil Armstrong <narmstrong@...libre.com>, Martin Blumenstingl <martin.blumenstingl@...glemail.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Kevin Hilman <khilman@...libre.com>, devicetree <devicetree@...r.kernel.org>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, linux-amlogic@...ts.infradead.org, Linux Kernel <linux-kernel@...r.kernel.org>, "open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org> Subject: Re: [PATCHv1 3/3] clk: meson: g12a: set cpu clock divider flags too CLK_IS_CRITICAL Hi Jerome, Thanks for your review comments. On Mon, 17 Feb 2020 at 13:32, Jerome Brunet <jbrunet@...libre.com> wrote: > > > On Sun 16 Feb 2020 at 18:34, Anand Moon <linux.amoon@...il.com> wrote: > > > Odroid N2 would fail to boot using microSD unless we set > > cpu freq clk divider flags to CLK_IS_CRITICAL to avoid stalling of > > cpu when booting, most likely because of PWM module linked to > > Where did you see a PWM ? > > > the CPU for DVFS is getting disabled in between the late_init call, > > between the late_init call and what ? > > > so gaiting the clock source shuts down the power to the codes. > > what code ? > > > Setting clk divider flags to CLK_IS_CRITICAL help resolve the issue. > > > > Cc: Martin Blumenstingl <martin.blumenstingl@...glemail.com> > > Cc: Jerome Brunet <jbrunet@...libre.com> > > Cc: Neil Armstrong <narmstrong@...libre.com> > > Suggested-by: Neil Armstrong <narmstrong@...libre.com> > > Signed-off-by: Anand Moon <linux.amoon@...il.com> > > --- > > > > Following Neil's suggestion, I have prepared this patch. > > https://patchwork.kernel.org/patch/11177441/#22964889 > > --- > > drivers/clk/meson/g12a.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c > > index d2760a021301..accae3695fe5 100644 > > --- a/drivers/clk/meson/g12a.c > > +++ b/drivers/clk/meson/g12a.c > > @@ -283,6 +283,7 @@ static struct clk_fixed_factor g12a_fclk_div2_div = { > > .ops = &clk_fixed_factor_ops, > > .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw }, > > .num_parents = 1, > > + .flags = CLK_IS_CRITICAL, > > This makes no sense for because: > * This clock cannot gate and none of its parents can either. IOW, the > output of this clock is never disabled. > * I cannot guess the relation between fdiv2 and the commit description > > > }, > > }; > > > > @@ -681,7 +682,7 @@ static struct clk_regmap g12b_cpub_clk = { > > &g12a_sys_pll.hw > > }, > > .num_parents = 2, > > - .flags = CLK_SET_RATE_PARENT, > > + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, > > Why not. Neil what do you think of this ? > If nothing is claiming this clock and enabling it then I suppose it > could make sense. > > > > }, > > }; > Sorry for the noise, I should not have send this patch in first place. -Anand
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