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Date: Mon, 17 Feb 2020 17:10:18 +0800 From: Bibby Hsieh <bibby.hsieh@...iatek.com> To: David Airlie <airlied@...ux.ie>, Matthias Brugger <matthias.bgg@...il.com>, Daniel Vetter <daniel.vetter@...ll.ch>, <dri-devel@...ts.freedesktop.org>, <linux-mediatek@...ts.infradead.org> CC: Philipp Zabel <p.zabel@...gutronix.de>, YT Shen <yt.shen@...iatek.com>, Thierry Reding <thierry.reding@...il.com>, CK Hu <ck.hu@...iatek.com>, <linux-arm-kernel@...ts.infradead.org>, <tfiga@...omium.org>, <drinkcat@...omium.org>, <linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com>, Bibby Hsieh <bibby.hsieh@...iatek.com>, Yongqiang Niu <yongqiang.niu@...iatek.com> Subject: [PATCH v1 1/3] arm64: dts: mt8183: Add gce setting in display node In order to use GCE function, we need add some information into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events). Signed-off-by: Bibby Hsieh <bibby.hsieh@...iatek.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com> --- This patch depends on ptach: [RESEND,v6,02/17] arm64: dts: add display nodes for mt8183 https://patchwork.kernel.org/patch/11316277/ --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index be4428c92f35..8b522b039a37 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/mt8183-power.h> +#include <dt-bindings/gce/mt8183-gce.h> #include "mt8183-pinfunc.h" / { @@ -664,6 +665,9 @@ reg = <0 0x14000000 0 0x1000>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; #clock-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; ovl0: ovl@...08000 { @@ -672,6 +676,7 @@ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; ovl_2l0: ovl@...09000 { @@ -680,6 +685,7 @@ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; ovl_2l1: ovl@...0a000 { @@ -688,6 +694,7 @@ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; rdma0: rdma@...0b000 { @@ -697,6 +704,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; mediatek,rdma_fifo_size = <5120>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; rdma1: rdma@...0c000 { @@ -706,6 +714,7 @@ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; mediatek,rdma_fifo_size = <2048>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; color0: color@...0e000 { @@ -715,6 +724,7 @@ interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_COLOR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; ccorr0: ccorr@...0f000 { @@ -723,6 +733,7 @@ interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_CCORR0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; aal0: aal@...10000 { @@ -732,6 +743,7 @@ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_AAL0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; gamma0: gamma@...11000 { @@ -741,6 +753,7 @@ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; dither0: dither@...12000 { @@ -749,6 +762,7 @@ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_DITHER0>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; mutex: mutex@...16000 { @@ -756,6 +770,8 @@ reg = <0 0x14016000 0 0x1000>; interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, + <CMDQ_EVENT_MUTEX_STREAM_DONE1>; }; smi_common: smi@...19000 { -- 2.18.0
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