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Date: Mon, 17 Feb 2020 19:13:40 +0800 From: Anson Huang <Anson.Huang@....com> To: robh+dt@...nel.org, mark.rutland@....com, shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com, devicetree@...r.kernel.org, u.kleine-koenig@...gutronix.de, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org Cc: Linux-imx@....com Subject: [PATCH V3 RESEND 6/7] ARM: dts: imx6sx-softing-vining-2000: Use new pin names with DCE/DTE for UART pins Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@....com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@...gutronix.de> --- No change. --- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 28563f2..61c7e72 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -384,15 +384,15 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; }; -- 2.7.4
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