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Message-ID: <158215607451.184098.15649983727508296275@swboyd.mtv.corp.google.com>
Date:   Wed, 19 Feb 2020 15:47:54 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     agross@...nel.org, bjorn.andersson@...aro.org,
        devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, mark.rutland@....com,
        robh+dt@...nel.org, sivaprak@...eaurora.org
Subject: Re: [PATCH] arm64: dts: ipq6018: Add a few device nodes

Quoting Sivaprakash Murugesan (2020-02-18 22:27:35)
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 0fb44e5..5d4dfb8 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -98,6 +121,36 @@
>                 dma-ranges;
>                 compatible = "simple-bus";
>  
> +               rng: qrng@...00 {

prng@...00?

> +                       compatible = "qcom,prng-ee";
> +                       reg = <0xe3000 0x1000>;
> +                       clocks = <&gcc GCC_PRNG_AHB_CLK>;
> +                       clock-names = "core";
> +               };
> +
> +               cryptobam: dma@...000 {
> +                       compatible = "qcom,bam-v1.7.0";
> +                       reg = <0x00704000 0x20000>;
> +                       interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
> +                       clock-names = "bam_clk";
> +                       #dma-cells = <1>;
> +                       qcom,ee = <1>;
> +                       qcom,controlled-remotely = <1>;
> +                       qcom,config-pipe-trust-reg = <0>;
> +               };
> @@ -146,6 +279,21 @@
>                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>                 };
>  
> +               watchdog@...7000 {
> +                       compatible = "qcom,kpss-wdt";
> +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

This isn't a rising edge interrupt?

> +                       reg = <0x0b017000 0x40>;
> +                       clocks = <&sleep_clk>;
> +                       timeout-sec = <10>;
> +               };
> +
> +               apcs_glb: mailbox@...1000 {
> +                       compatible = "qcom,ipq8074-apcs-apps-global";
> +                       reg = <0x0b111000 0xc>;
> +
> +                       #mbox-cells = <1>;
> +               };
> +
>                 timer {
>                         compatible = "arm,armv8-timer";
>                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -213,5 +361,85 @@
>                         };
>                 };
>  
> +               q6v5_wcss: q6v5_wcss@...0000 {

remoteproc@...0000?

> +                       compatible = "qcom,ipq8074-wcss-pil";
> +                       reg = <0x0cd00000 0x4040>,
> +                               <0x004ab000 0x20>;
> +                       reg-names = "qdsp6",
> +                                   "rmb";
[...]
> +                       glink-edge {
> +                               interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
> +                               qcom,remote-pid = <1>;
> +                               mboxes = <&apcs_glb 8>;
> +
> +                               rpm_requests {
> +                                       qcom,glink-channels = "IPCRTR";
> +                               };
> +                       };
> +               };
> +
> +       };
> +
> +       tcsr_mutex: tcsr-mutex {

hwlock?

> +               compatible = "qcom,tcsr-mutex";
> +               syscon = <&tcsr_mutex_regs 0 0x80>;
> +               #hwlock-cells = <1>;
> +       };
> +

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