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Message-ID: <e9f7eaac-5b61-1662-2ae1-924d126e6a97@linaro.org>
Date: Thu, 20 Feb 2020 10:38:00 +0100
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: Benjamin Gaignard <benjamin.gaignard@...com>, lee.jones@...aro.org,
robh+dt@...nel.org, mark.rutland@....com,
mcoquelin.stm32@...il.com, alexandre.torgue@...com,
tglx@...utronix.de, fabrice.gasnier@...com
Cc: devicetree@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/3] mfd: stm32: Add defines to be used for clkevent
purpose
Hi Lee,
On 17/02/2020 14:45, Benjamin Gaignard wrote:
> Add defines to be able to enable/clear irq and configure one shot mode.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@...com>
Are you fine if I pick this patch with the series?
> ---
> version 4:
> - move defines in mfd/stm32-lptimer.h
>
> include/linux/mfd/stm32-lptimer.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lptimer.h
> index 605f62264825..90b20550c1c8 100644
> --- a/include/linux/mfd/stm32-lptimer.h
> +++ b/include/linux/mfd/stm32-lptimer.h
> @@ -27,10 +27,15 @@
> #define STM32_LPTIM_CMPOK BIT(3)
>
> /* STM32_LPTIM_ICR - bit fields */
> +#define STM32_LPTIM_ARRMCF BIT(1)
> #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)
>
> +/* STM32_LPTIM_IER - bit flieds */
> +#define STM32_LPTIM_ARRMIE BIT(1)
> +
> /* STM32_LPTIM_CR - bit fields */
> #define STM32_LPTIM_CNTSTRT BIT(2)
> +#define STM32_LPTIM_SNGSTRT BIT(1)
> #define STM32_LPTIM_ENABLE BIT(0)
>
> /* STM32_LPTIM_CFGR - bit fields */
>
--
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