linux-kernel - RE: [PATCH RESEND v3 4/4] clk: imx: imx8mp: fix a53 cpu clock

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Date:   Mon, 24 Feb 2020 01:13:35 +0000
From:   Peng Fan <peng.fan@....com>
To:     "sboyd@...nel.org" <sboyd@...nel.org>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        Abel Vesa <abel.vesa@....com>,
        Leonard Crestez <leonard.crestez@....com>
CC:     "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>,
        Aisheng Dong <aisheng.dong@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Anson Huang <anson.huang@....com>,
        Jacky Bai <ping.bai@....com>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>
Subject: RE: [PATCH RESEND v3 4/4] clk: imx: imx8mp: fix a53 cpu clock

Hi Shawn,

> Subject: [PATCH RESEND v3 4/4] clk: imx: imx8mp: fix a53 cpu clock

Would you pick up this? Without this patch, i.MX8MP will hang when
booting.

Thanks,
Peng.
> 
> From: Peng Fan <peng.fan@....com>
> 
> The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff
> timing is 1Ghz, however the A53 core which sources from CCM root could run
> above 1GHz which voilates the CCM.
> 
> There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL
> slice source from ARM PLL, not A53 CCM clk root.
> 
> The A53 CCM clk root should only be used when need to change ARM PLL
> frequency.
> 
> Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
> Configure a53 ccm root sources from 800MHz sys pll Configure a53 core
> sources from arm_pll_out Mark arm_a53_core as critical clk
> 
> Reviewed-by: Jacky Bai <ping.bai@....com>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
>  drivers/clk/imx/clk-imx8mp.c             | 16 ++++++++++++----
>  include/dt-bindings/clock/imx8mp-clock.h |  3 ++-
>  2 files changed, 14 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index a16af4fce044..d67ee36b84de 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -34,6 +34,8 @@ static const char * const imx8mp_a53_sels[] =
> {"osc_24m", "arm_pll_out", "sys_pl
>  					       "sys_pll2_1000m", "sys_pll1_800m",
> "sys_pll1_400m",
>  					       "audio_pll1_out", "sys_pll3_out", };
> 
> +static const char * const imx8mp_a53_core_sels[] = {"arm_a53_div",
> +"arm_pll_out", };
> +
>  static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m",
> "sys_pll2_250m",
>  					      "vpu_pll_out", "sys_pll1_800m",
> "audio_pll1_out",
>  					      "video_pll1_out", "sys_pll3_out", }; @@
> -554,6 +556,9 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
>  	hws[IMX8MP_CLK_HSIO_AXI_DIV] =
> imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3);
>  	hws[IMX8MP_CLK_MEDIA_ISP_DIV] =
> imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400,
> 0, 3);
> 
> +	/* CORE SEL */
> +	hws[IMX8MP_CLK_A53_CORE] =
> imx_clk_hw_mux2_flags("arm_a53_core",
> +ccm_base + 0x9880, 24, 1, imx8mp_a53_core_sels,
> +ARRAY_SIZE(imx8mp_a53_core_sels), CLK_IS_CRITICAL);
> +
>  	hws[IMX8MP_CLK_MAIN_AXI] =
> imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels,
> ccm_base + 0x8800);
>  	hws[IMX8MP_CLK_ENET_AXI] = imx8m_clk_hw_composite("enet_axi",
> imx8mp_enet_axi_sels, ccm_base + 0x8880);
>  	hws[IMX8MP_CLK_NAND_USDHC_BUS] =
> imx8m_clk_hw_composite_critical("nand_usdhc_bus",
> imx8mp_nand_usdhc_sels, ccm_base + 0x8900); @@ -724,11 +729,14 @@
> static int imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk",
> "vpu_bus", ccm_base + 0x4630, 0);
>  	hws[IMX8MP_CLK_AUDIO_ROOT] =
> imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0);
> 
> -	hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_div",
> -					     hws[IMX8MP_CLK_A53_DIV]->clk,
> -					     hws[IMX8MP_CLK_A53_SRC]->clk,
> +	clk_hw_set_parent(hws[IMX8MP_CLK_A53_SRC],
> hws[IMX8MP_SYS_PLL1_800M]);
> +	clk_hw_set_parent(hws[IMX8MP_CLK_A53_CORE],
> hws[IMX8MP_ARM_PLL_OUT]);
> +
> +	hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
> +					     hws[IMX8MP_CLK_A53_CORE]->clk,
> +					     hws[IMX8MP_CLK_A53_CORE]->clk,
>  					     hws[IMX8MP_ARM_PLL_OUT]->clk,
> -					     hws[IMX8MP_SYS_PLL1_800M]->clk);
> +					     hws[IMX8MP_CLK_A53_DIV]->clk);
> 
>  	imx_check_clk_hws(hws, IMX8MP_CLK_END);
> 
> diff --git a/include/dt-bindings/clock/imx8mp-clock.h
> b/include/dt-bindings/clock/imx8mp-clock.h
> index 2fab63186bca..c92d1f4117eb 100644
> --- a/include/dt-bindings/clock/imx8mp-clock.h
> +++ b/include/dt-bindings/clock/imx8mp-clock.h
> @@ -294,7 +294,8 @@
>  #define IMX8MP_CLK_DRAM_ALT_ROOT		285
>  #define IMX8MP_CLK_DRAM_CORE			286
>  #define IMX8MP_CLK_ARM				287
> +#define IMX8MP_CLK_A53_CORE			288
> 
> -#define IMX8MP_CLK_END				288
> +#define IMX8MP_CLK_END				289
> 
>  #endif
> --
> 2.16.4