linux-kernel - Re: [PATCH RFC] mmc: sdhci-msm: Toggle fifo write clk after ungating sdcc clk

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Message-ID: <4e4f1e44-8033-94e9-641c-a74232727895@codeaurora.org>
Date:   Mon, 24 Feb 2020 19:19:58 +0530
From:   Veerabhadrarao Badiganti <vbadigan@...eaurora.org>
To:     Sayali Lokhande <sayalil@...eaurora.org>,
        bjorn.andersson@...aro.org, adrian.hunter@...el.com,
        robh+dt@...nel.org, ulf.hansson@...aro.org,
        asutoshd@...eaurora.org, stummala@...eaurora.org,
        ppvk@...eaurora.org, rampraka@...eaurora.org, sboyd@...nel.org,
        georgi.djakov@...aro.org, mka@...omium.org
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        agross@...nel.org, linux-mmc-owner@...r.kernel.org
Subject: Re: [PATCH RFC] mmc: sdhci-msm: Toggle fifo write clk after ungating
 sdcc clk


On 2/20/2020 2:50 PM, Sayali Lokhande wrote:
> From: Ram Prakash Gupta <rampraka@...eaurora.org>
>
> During GCC level clock gating of MCLK, the async FIFO
> gets into some hang condition, such that for the next
> transfer after MCLK ungating, first bit of CMD response
> doesn't get written in to the FIFO. This cause the CPSM
> to hang eventually leading to SW timeout.
>
> To fix the issue, toggle the FIFO write clock after
> MCLK ungated to get the FIFO pointers and flags to
> valid states.
>
> Change-Id: Ibef2d1d283ac0b6983c609a4abc98bc574d31fa6
> Signed-off-by: Ram Prakash Gupta <rampraka@...eaurora.org>
> Signed-off-by: Sayali Lokhande <sayalil@...eaurora.org>
> ---
>   drivers/mmc/host/sdhci-msm.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 43 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index c3a160c..eaa3e95 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -127,6 +127,8 @@
>   #define CQHCI_VENDOR_CFG1	0xA00
>   #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN	(0x3 << 13)
>   
> +#define RCLK_TOGGLE 0x2
> +
>   struct sdhci_msm_offset {
>   	u32 core_hc_mode;
>   	u32 core_mci_data_cnt;
> @@ -1554,6 +1556,43 @@ static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>   	sdhci_enable_clk(host, clk);
>   }
>   
> +/*
> + * After MCLK ugating, toggle the FIFO write clock to get
> + * the FIFO pointers and flags to valid state.
> + */
> +static void sdhci_msm_toggle_fifo_write_clk(struct sdhci_host *host)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
> +	const struct sdhci_msm_offset *msm_offset =
> +					msm_host->offset;
> +	struct mmc_card *card = host->mmc->card;
> +
> +	if (msm_host->tuning_done ||
> +			(card && card->ext_csd.strobe_support &&
> +			card->host->ios.enhanced_strobe)) {

This issue is present on only HS400ES mode.

If(host->ios.enhanced_strob) check should be sufficient, other checks 
are not needed.

> +		/*
> +		 * set HC_REG_DLL_CONFIG_3[1] to select MCLK as
> +		 * DLL input clock
> +		 */
> +		writel_relaxed(((readl_relaxed(host->ioaddr +
> +			msm_offset->core_dll_config_3))
> +			| RCLK_TOGGLE), host->ioaddr +
> +			msm_offset->core_dll_config_3);
> +		/* ensure above write as toggling same bit quickly */
> +		wmb();
> +		udelay(2);
> +		/*
> +		 * clear HC_REG_DLL_CONFIG_3[1] to select RCLK as
> +		 * DLL input clock
> +		 */
> +		writel_relaxed(((readl_relaxed(host->ioaddr +
> +			msm_offset->core_dll_config_3))
> +			& ~RCLK_TOGGLE), host->ioaddr +
> +			msm_offset->core_dll_config_3);
> +	}
> +}
> +
>   /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
>   static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>   {
> @@ -2149,6 +2188,10 @@ static __maybe_unused int sdhci_msm_runtime_resume(struct device *dev)
>   				       msm_host->bulk_clks);
>   	if (ret)
>   		return ret;
> +	if (host->mmc &&
> +			(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
These checks are not needed. You can have these checks within 
sdhci_msm_toggle_fifo_write_clk
> +		sdhci_msm_toggle_fifo_write_clk(host);
> +
>   	/*
>   	 * Whenever core-clock is gated dynamically, it's needed to
>   	 * restore the SDR DLL settings when the clock is ungated.