linux-kernel - Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver

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Date:   Tue, 25 Feb 2020 16:30:21 +0530
From:   Vignesh Raghavendra <vigneshr@...com>
To:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>,
        Rob Herring <robh+dt@...nel.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        Mark Brown <broonie@...nel.org>,
        <simon.k.r.goldschmidt@...il.com>,
        Dinh Nguyen <dinguyen@...nel.org>, <tien.fong.chee@...el.com>,
        Marek Vašut <marex@...x.de>,
        <cheol.yong.kim@...el.com>, <qi-ming.wu@...el.com>
Subject: Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI
 Controller driver



On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote:
>>>>> +
>>>>> +  cdns,fifo-depth:
>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>> +    description:
>>>>> +      Size of the data FIFO in words.
>>>> A 4GB fifo is valid? Add some constraints.
>>> 128 is valid, will update.
>> Nope, the width of this field is 8bits -> 256 bytes 
> 
> correct me if I am wrong, the width of this field is 4bits -> 128 bytes
> (based on QUAD mode) .

This has nothing to do with quad-mode. Its about how much SRAM amount of
SRAM is present to buffer INDAC mode data. For TI platforms this is 256
bytes.
See CQSPI_REG_SRAMPARTITION definition in your datasheet.

-- 
Regards
Vignesh