lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 25 Feb 2020 04:35:21 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Stephen Warren <swarren@...dotorg.org>
Cc:     Jens Axboe <axboe@...nel.dk>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Michał Mirosław <mirq-linux@...e.qmqm.pl>,
        David Heidelberg <david@...t.cz>,
        Peter Geis <pgwipeout@...il.com>,
        Nicolas Chauvet <kwizart@...il.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Billy Laws <blaws05@...il.com>, linux-tegra@...r.kernel.org,
        linux-block@...r.kernel.org, Andrey Danin <danindrey@...l.ru>,
        Gilles Grandou <gilles@...ndou.net>,
        Ryan Grachek <ryan@...ted.us>, linux-mmc@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 3/3] partitions: Introduce NVIDIA Tegra Partition Table

25.02.2020 03:20, Stephen Warren пишет:
> On 2/24/20 4:18 PM, Dmitry Osipenko wrote:
>> All NVIDIA Tegra devices use a special partition table format for the
>> internal storage partitioning. Most of Tegra devices have GPT partition
>> in addition to TegraPT, but some older Android consumer-grade devices do
>> not or GPT is placed in a wrong sector, and thus, the TegraPT is needed
>> in order to support these devices properly in the upstream kernel. This
>> patch adds support for NVIDIA Tegra Partition Table format that is used
>> at least by all NVIDIA Tegra20 and Tegra30 devices.
> 
>> diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
> 
>> +static void __init tegra_boot_config_table_init(void)
>> +{
>> +    void __iomem *bct_base;
>> +    u16 pt_addr, pt_size;
>> +
>> +    bct_base = IO_ADDRESS(TEGRA_IRAM_BASE) + TEGRA_IRAM_BCT_OFFSET;
> 
> This shouldn't be hard-coded. IIRC, the boot ROM writes a BIT (Boot
> Information Table) to a fixed location in IRAM, and there's some value
> in the BIT that points to where the BCT is in IRAM. In practice, it
> might work out that the BCT is always at the same place in IRAM, but
> this certainly isn't guaranteed. I think there's code in U-Boot which
> extracts the BCT location from the BIT? Yes, see
> arch/arm/mach-tegra/ap.c:get_odmdata().

Thank you very much, I didn't know about that.

I checked whether Nexus 7 and A500 have a correct pointer in the BIT and
they have it. I'll take it into account in v2, thank you again.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ