linux-kernel - Re: [PATCH v5 5/5] clk: qcom: Add modem clock controller driver for SC7180

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Date:   Tue, 25 Feb 2020 16:20:33 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Michael Turquette <mturquette@...libre.com>,
        Taniya Das <tdas@...eaurora.org>
Cc:     David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Andy Gross <agross@...nel.org>, devicetree@...r.kernel.org,
        robh@...nel.org, robh+dt@...nel.org,
        Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v5 5/5] clk: qcom: Add modem clock controller driver for SC7180

Quoting Taniya Das (2020-02-24 02:38:23)
> diff --git a/drivers/clk/qcom/mss-sc7180.c b/drivers/clk/qcom/mss-sc7180.c
> new file mode 100644
> index 0000000..993749e
> --- /dev/null
> +++ b/drivers/clk/qcom/mss-sc7180.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>

Is this used?

> +#include <linux/pm_clock.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,mss-sc7180.h>
> +
> +#include "clk-regmap.h"
> +#include "clk-branch.h"
> +#include "common.h"
> +
> +static struct clk_branch mss_axi_nav_clk = {
> +       .halt_reg = 0x20bc,
> +       .halt_check = BRANCH_HALT,
> +       .clkr = {
> +               .enable_reg = 0x20bc,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "mss_axi_nav_clk",
> +                       .parent_data = &(const struct clk_parent_data){
> +                               .fw_name = "gcc_mss_nav_axi_clk",
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static struct clk_branch mss_axi_crypto_clk = {
> +       .halt_reg = 0x20cc,
> +       .halt_check = BRANCH_HALT,
> +       .clkr = {
> +               .enable_reg = 0x20cc,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "mss_axi_crypto_clk",
> +                       .parent_data = &(const struct clk_parent_data){
> +                               .fw_name = "gcc_mss_mfab_axis_clk",
> +                       },
> +                       .num_parents = 1,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
> +static const struct regmap_config mss_regmap_config = {
> +       .reg_bits       = 32,
> +       .reg_stride     = 4,
> +       .val_bits       = 32,
> +       .fast_io        = true,

What is the max register?

> +};
> +
> +static struct clk_regmap *mss_sc7180_clocks[] = {
> +       [MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
> +       [MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
> +};