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Message-Id: <20200226220213.27423-1-atish.patra@wdc.com>
Date: Wed, 26 Feb 2020 14:02:01 -0800
From: Atish Patra <atish.patra@....com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atish.patra@....com>,
Albert Ou <aou@...s.berkeley.edu>,
Alexios Zavras <alexios.zavras@...el.com>,
Anup Patel <anup@...infault.org>, Borislav Petkov <bp@...e.de>,
Daniel Jordan <daniel.m.jordan@...cle.com>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
Gary Guo <gary@...yguo.net>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Greentime Hu <greentime.hu@...ive.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Heiko Carstens <heiko.carstens@...ibm.com>,
Jason Cooper <jason@...edaemon.net>,
Kate Stewart <kstewart@...uxfoundation.org>,
Kees Cook <keescook@...omium.org>,
linux-riscv@...ts.infradead.org,
Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>,
Mao Han <han_mao@...ky.com>, Marc Zyngier <maz@...nel.org>,
Michael Kelley <mikelley@...rosoft.com>,
Mike Rapoport <rppt@...ux.ibm.com>,
Nick Hu <nickhu@...estech.com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
Steven Price <steven.price@....com>,
Sudeep Holla <sudeep.holla@....com>,
Thomas Gleixner <tglx@...utronix.de>,
Vincent Chen <vincent.chen@...ive.com>,
Zong Li <zong.li@...ive.com>
Subject: [PATCH v10 00/12] Add support for SBI v0.2 and CPU hotplug
The Supervisor Binary Interface(SBI) specification[1] now defines a
base extension that provides extendability to add future extensions
while maintaining backward compatibility with previous versions.
The new version is defined as 0.2 and older version is marked as 0.1.
This series adds following features to RISC-V Linux.
1. Adds support for SBI v0.2
2. A Unified calling convention implementation between 0.1 and 0.2.
3. SBI Hart state management extension (HSM)
4. Ordered booting of harts
4. CPU hotplug
Dependencies:
The support for SBI v0.2 and HSM extension is already available in OpenSBI
master.
[1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
The patches are also available in following github repositery.
Linux Kernel: https://github.com/atishp04/linux/tree/sbi_v0.2_v10
Patches 1-5 implements the SBI v0.2 and unified calling convention.
Patches 6-7 adds a cpu_ops method that allows different booting protocols
dynamically.
Patches 9-10 adds HSM extension and ordered hart booting support.
Patche 11 adds cpu hotplug support.
Changes from v9->10:
1. Minor copyright fixes.
2. Renaming of HSM extension definitions to match the spec.
Changes from v8->v9:
1. Added a sliding window hart base method to support larger hart masks.
2. Added a callback to disable interrupts when cpu go offline.
3. Made the HSM extension series more modular.
Changes from v7-v8:
1. Refactored to code to have modular cpu_ops calls.
2. Refactored HSM extension from sbi.c to cpu_ops_sbi.c.
3. Fix plic driver to handle cpu hotplug.
Changes from v6-v7:
1. Rebased on v5.5
2. Fixed few compilation issues for !CONFIG_SMP and !CONFIG_RISCV_SBI
3. Added SBI HSM extension
4. Add CPU hotplug support
Changes from v5->v6
1. Fixed few compilation issues around config.
2. Fixed hart mask generation issues for RFENCE & IPI extensions.
Changes from v4->v5
1. Fixed few minor comments related to static & inline.
2. Make sure that every patch is boot tested individually.
Changes from v3->v4.
1. Rebased on for-next.
2. Fixed issuses with checkpatch --strict.
3. Unfied all IPI/fence related functions.
4. Added Hfence related SBI calls.
Changes from v2->v3.
1. Moved v0.1 extensions to a new config.
2. Added support for relacement extensions of v0.1 extensions.
Changes from v1->v2
1. Removed the legacy calling convention.
2. Moved all SBI related calls to sbi.c.
3. Moved all SBI related macros to uapi.
Atish Patra (12):
RISC-V: Mark existing SBI as 0.1 SBI.
RISC-V: Add basic support for SBI v0.2
RISC-V: Add SBI v0.2 extension definitions
RISC-V: Introduce a new config for SBI v0.1
RISC-V: Implement new SBI v0.2 extensions
RISC-V: Move relocate and few other functions out of __init
RISC-V: Add cpu_ops and modify default booting method
RISC-V: Export SBI error to linux error mapping function
RISC-V: Add SBI HSM extension definitions
RISC-V: Add supported for ordered booting method using HSM
RISC-V: Support cpu hotplug
irqchip/sifive-plic: Initialize the plic handler when cpu comes online
arch/riscv/Kconfig | 19 +-
arch/riscv/include/asm/cpu_ops.h | 46 +++
arch/riscv/include/asm/sbi.h | 194 +++++----
arch/riscv/include/asm/smp.h | 24 ++
arch/riscv/kernel/Makefile | 6 +
arch/riscv/kernel/cpu-hotplug.c | 87 ++++
arch/riscv/kernel/cpu_ops.c | 46 +++
arch/riscv/kernel/cpu_ops_sbi.c | 115 ++++++
arch/riscv/kernel/cpu_ops_spinwait.c | 42 ++
arch/riscv/kernel/head.S | 179 +++++----
arch/riscv/kernel/sbi.c | 567 ++++++++++++++++++++++++++-
arch/riscv/kernel/setup.c | 24 +-
arch/riscv/kernel/smpboot.c | 53 +--
arch/riscv/kernel/traps.c | 4 +-
arch/riscv/kernel/vmlinux.lds.S | 5 +-
drivers/irqchip/irq-sifive-plic.c | 38 +-
include/linux/cpuhotplug.h | 1 +
17 files changed, 1275 insertions(+), 175 deletions(-)
create mode 100644 arch/riscv/include/asm/cpu_ops.h
create mode 100644 arch/riscv/kernel/cpu-hotplug.c
create mode 100644 arch/riscv/kernel/cpu_ops.c
create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c
create mode 100644 arch/riscv/kernel/cpu_ops_spinwait.c
--
2.25.0
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