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Message-Id: <20200227181452.31558-5-thirtythreeforty@gmail.com>
Date: Thu, 27 Feb 2020 12:14:51 -0600
From: George Hilliard <thirtythreeforty@...il.com>
To: Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Cc: Icenowy Zheng <icenowy@...c.io>, linux-kernel@...r.kernel.org,
George Hilliard <thirtythreeforty@...il.com>
Subject: [PATCH 4/5] ARM: suniv: add USB-related device nodes
From: Icenowy Zheng <icenowy@...c.io>
The suniv SoC has a USB OTG controller and a USB PHY like other
Allwinner SoCs.
Add their device tree node.
Signed-off-by: Icenowy Zheng <icenowy@...c.io>
Signed-off-by: George Hilliard <thirtythreeforty@...il.com>
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 29 ++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 6100d3b75f61..ec9f248ba889 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -4,6 +4,9 @@
* Copyright 2018 Mesih Kilinc <mesihkilinc@...il.com>
*/
+#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
+#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
+
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -140,5 +143,31 @@ uart2: serial@...5800 {
resets = <&ccu 26>;
status = "disabled";
};
+
+ usb_otg: usb@...3000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@...3400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
};
};
--
2.25.0
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