linux-kernel - RE: [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP DDRC binding doc

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Date:   Thu, 27 Feb 2020 06:40:33 +0000
From:   Sherry Sun <sherry.sun@....com>
To:     Rob Herring <robh@...nel.org>
CC:     "bp@...en8.de" <bp@...en8.de>,
        "mchehab@...nel.org" <mchehab@...nel.org>,
        "tony.luck@...el.com" <tony.luck@...el.com>,
        "james.morse@....com" <james.morse@....com>,
        "rrichter@...vell.com" <rrichter@...vell.com>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        dl-linux-imx <linux-imx@....com>, Frank Li <frank.li@....com>
Subject: RE: [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP DDRC
 binding doc

Hi Rob,

> -----Original Message-----
> From: linux-kernel-owner@...r.kernel.org <linux-kernel-
> owner@...r.kernel.org> On Behalf Of Rob Herring
> Sent: 2020年2月27日 1:25
> To: Sherry Sun <sherry.sun@....com>
> Cc: bp@...en8.de; mchehab@...nel.org; tony.luck@...el.com;
> james.morse@....com; rrichter@...vell.com; michal.simek@...inx.com;
> shawnguo@...nel.org; s.hauer@...gutronix.de; mark.rutland@....com;
> linux-edac@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; dl-linux-imx
> <linux-imx@....com>; Frank Li <frank.li@....com>
> Subject: Re: [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP
> DDRC binding doc
> 
> On Fri, Feb 21, 2020 at 02:39:14PM +0800, sherry sun wrote:
> > From: Sherry Sun <sherry.sun@....com>
> >
> > Add documentation for i.MX8MP DDRC binding based on synopsys_edac
> doc,
> > which use the same memory-controller IP.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@....com>
> > ---
> >  .../devicetree/bindings/memory-controllers/synopsys.txt   | 8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
> > b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
> > index 9d32762c47e1..5c03959a451f 100644
> > ---
> > a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt
> > +++ b/Documentation/devicetree/bindings/memory-
> controllers/synopsys.tx
> > +++ t
> > @@ -6,16 +6,20 @@ bus width configurations.
> >  The Zynq DDR ECC controller has an optional ECC support in half-bus
> > width
> >  (16-bit) configuration.
> >
> > -These both ECC controllers correct single bit ECC errors and detect
> > double bit
> > +The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width
> > +configurations.
> > +
> > +These all ECC controllers correct single bit ECC errors and detect
> > +double bit
> 
> All the ECC...
> 
> With that,
> 
> Reviewed-by: Rob Herring <robh@...nel.org>

Thanks, I will correct it.

Best regards
Sherry Sun

> 
> >  ECC errors.
> >
> >  Required properties:
> >   - compatible: One of:
> >  	- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
> >  	- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
> > +	- 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller
> >   - reg: Should contain DDR controller registers location and length.
> >
> > -Required properties for "xlnx,zynqmp-ddrc-2.40a":
> > +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc":
> >   - interrupts: Property with a value describing the interrupt number.
> >
> >  Example:
> > --
> > 2.17.1
> >