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Message-ID: <1582789610-23133-2-git-send-email-sam.shih@mediatek.com>
Date: Thu, 27 Feb 2020 15:46:50 +0800
From: Sam Shih <sam.shih@...iatek.com>
To: Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
Matthias Brugger <matthias.bgg@...il.com>
CC: John Crispin <john@...ozen.org>, <linux-pwm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
Sam Shih <sam.shih@...iatek.com>
Subject: [PATCH 1/1] pwm: mediatek: add longer period support
The pwm clock source could be divided by 1625 with PWM_CON
BIT(3) setting in mediatek hardware.
This patch add support for longer pwm period configuration,
which allowing blinking LEDs via pwm interface.
Signed-off-by: Sam Shih <sam.shih@...iatek.com>
---
drivers/pwm/pwm-mediatek.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index b94e0d09c300..9af309bea01a 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -121,8 +121,8 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
- u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
- reg_thres = PWMTHRES;
+ u32 clkdiv = 0, clksel = 0, cnt_period, cnt_duty,
+ reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
u64 resolution;
int ret;
@@ -141,9 +141,18 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
clkdiv++;
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000,
resolution);
+ if (clkdiv > PWM_CLK_DIV_MAX && !clksel) {
+ clksel = 1;
+ clkdiv = 0;
+ resolution = (u64)NSEC_PER_SEC * 1000 * 1625;
+ do_div(resolution,
+ clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
+ cnt_period = DIV_ROUND_CLOSEST_ULL(
+ (u64)period_ns * 1000, resolution);
+ }
}
- if (clkdiv > PWM_CLK_DIV_MAX) {
+ if (clkdiv > PWM_CLK_DIV_MAX && clksel) {
pwm_mediatek_clk_disable(chip, pwm);
dev_err(chip->dev, "period %d not supported\n", period_ns);
return -EINVAL;
@@ -159,7 +168,11 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
}
cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution);
- pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
+ if (clksel)
+ pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) |
+ clkdiv);
+ else
+ pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
--
2.17.1
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