linux-kernel - Re: [RFC net-next 3/3] dt-bindings: marvell,prestera: Add address mapping for Prestera Switchdev PCIe driver

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Date:   Thu, 27 Feb 2020 20:24:04 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Vadym Kochan <vadym.kochan@...ision.eu>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "David S . Miller" <davem@...emloft.net>
Cc:     Oleksandr Mazur <oleksandr.mazur@...ision.eu>,
        Taras Chornyi <taras.chornyi@...ision.eu>,
        Serhiy Boiko <serhiy.boiko@...ision.eu>,
        Andrii Savka <andrii.savka@...ision.eu>,
        Volodymyr Mytnyk <volodymyr.mytnyk@...ision.eu>
Subject: Re: [RFC net-next 3/3] dt-bindings: marvell,prestera: Add address
 mapping for Prestera Switchdev PCIe driver



On 2/25/2020 8:30 AM, Vadym Kochan wrote:
> Document requirement for the PCI port which is connected to the ASIC, to
> allow access to the firmware related registers.
> 
> Signed-off-by: Vadym Kochan <vadym.kochan@...ision.eu>
> ---
>  .../devicetree/bindings/net/marvell,prestera.txt    | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt
> index 83370ebf5b89..103c35cfa8a7 100644
> --- a/Documentation/devicetree/bindings/net/marvell,prestera.txt
> +++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt
> @@ -45,3 +45,16 @@ dfx-server {
>  	ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
>  	reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
>  };
> +
> +Marvell Prestera SwitchDev bindings
> +-----------------------------------
> +The current implementation of Prestera Switchdev PCI interface driver requires
> +that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:

It is always a bit disturbing to document what a driver does, or want in
a Device Tree binding. If it is necessary for the PCIe device to have
multiple ranges defined such that the necessary BARs are available, that
is what is necessary, no need to mention what the driver or firmware does.

> +
> +&cp0_pcie0 {
> +	ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
> +		0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
> +		0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
> +	phys = <&cp0_comphy0 0>;
> +	status = "okay";
> +};
> 

-- 
Florian