linux-kernel - [PATCH v10 1/5] dt-bindings: media: add pclk-sample dual edge property

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Message-ID: <20200228052128.82136-2-jitao.shi@mediatek.com>
Date:   Fri, 28 Feb 2020 13:21:24 +0800
From:   Jitao Shi <jitao.shi@...iatek.com>
To:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Daniel Vetter <daniel@...ll.ch>,
        David Airlie <airlied@...ux.ie>,
        <dri-devel@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
CC:     <linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <srv_heupstream@...iatek.com>, <yingjoe.chen@...iatek.com>,
        <eddie.huang@...iatek.com>, <cawa.cheng@...iatek.com>,
        <bibby.hsieh@...iatek.com>, <ck.hu@...iatek.com>,
        <stonea168@....com>, <huijuan.xie@...iatek.com>,
        Jitao Shi <jitao.shi@...iatek.com>,
        Rob Herring <robh@...nel.org>
Subject: [PATCH v10 1/5] dt-bindings: media: add pclk-sample dual edge property

Some chips's sample mode are rising, falling and dual edge (both
falling and rising edge).
Extern the pclk-sample property to support dual edge.

Acked-by: Rob Herring <robh@...nel.org>
Reviewed-by: CK Hu <ck.hu@...iatek.com>
Signed-off-by: Jitao Shi <jitao.shi@...iatek.com>
---
 Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt
index f884ada0bffc..da9ad24935db 100644
--- a/Documentation/devicetree/bindings/media/video-interfaces.txt
+++ b/Documentation/devicetree/bindings/media/video-interfaces.txt
@@ -118,8 +118,8 @@ Optional endpoint properties
 - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable
   signal polarity.
 - field-even-active: field signal level during the even field data transmission.
-- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
-  signal.
+- pclk-sample: sample data on rising (1), falling (0) or both rising and
+  falling (2) edge of the pixel clock signal.
 - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for
   LOW/HIGH respectively.
 - data-lanes: an array of physical data lane indexes. Position of an entry
-- 
2.21.0