lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Fri, 28 Feb 2020 15:53:37 +0800
From:   "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>
To:     Boris Brezillon <boris.brezillon@...labora.com>
Cc:     linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
        broonie@...nel.org, vigneshr@...com, robh+dt@...nel.org,
        marex@...x.de, devicetree@...r.kernel.org,
        tien.fong.chee@...el.com, tudor.ambarus@...il.com,
        boris.brezillon@...e-electrons.com, richard@....at,
        qi-ming.wu@...el.com, simon.k.r.goldschmidt@...il.com,
        david.oberhollenzer@...ma-star.at, dinguyen@...nel.org,
        linux-mtd@...ts.infradead.org, miquel.raynal@...tlin.com,
        cheol.yong.kim@...el.com, mark.rutland@....com,
        computersforpeace@...il.com, dwmw2@...radead.org,
        cyrille.pitchen@...el.com
Subject: Re: [PATCH v11 2/2] spi: cadence-quadspi: Add support for the Cadence
 QSPI controller

Hi Boris,

On 28/2/2020 3:46 PM, Boris Brezillon wrote:
> On Fri, 28 Feb 2020 12:11:09 +0800
> "Ramuthevar, Vadivel MuruganX"
> <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote:
>
>> Hi Boris,
>>
>>        Thank you so much for the review comments...
>>
>> On 28/2/2020 1:30 AM, Boris Brezillon wrote:
>>> On Thu, 27 Feb 2020 14:27:08 +0800
>>> "Ramuthevar, Vadivel MuruganX"
>>> <vadivel.muruganx.ramuthevar@...ux.intel.com> wrote:
>>>   
>>>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@...ux.intel.com>
>>>>
>>>> Add support for the Cadence QSPI controller. This controller is
>>>> present in the Intel Lightning Mountain(LGM) SoCs, Altera and TI SoCs.
>>>> This driver has been tested on the Intel LGM SoCs.
>>>>
>>>> This driver does not support generic SPI and also the implementation
>>>> only supports spi-mem interface to replace the existing driver in
>>>> mtd/spi-nor/cadence-quadspi.c, the existing driver only support SPI-NOR
>>>> flash memory
>>> Is it really supporting SPI NORs only, or is it just that you only
>>> tested it with a spi-nor?
>> The existing drivers/mtd/spi-nor/cadence-quadspi.c supports SPI-NORs
>> only, because the driver is developed
>>
>> such a way that it does not support other SPI based flash memories, also
>> never uses SPI/SPI-MEM based framework.
>>
>> So we Vignesh suggested me to  develop the new driver which supports
>> both SPI-NOR and SPI-NAND based on the SPI-MEM framework.
> Hm, your commit message makes it sound like even the new driver isn't
> generic enough to support SPI NANDs. Maybe there's something to improve
> to clarify the fact that this new version is not limited to SPI NORs.

Thanks! for the suggestions to remind me to add.

sure, I will add more information about supporting SPI-NOR and SPI-NAND

Regards
Vadivel

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ