linux-kernel - Re: [PATCH v4 2/3] dt-bindings: phy: Add YAML schemas for Intel Combophy

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAL_JsqLKFbaiaeNAq_b9xDQRWVG8dXkWt2+cKucRPEzynC20XQ@mail.gmail.com>
Date:   Tue, 3 Mar 2020 10:26:33 -0600
From:   Rob Herring <robh@...nel.org>
To:     Dilip Kota <eswara.kota@...ux.intel.com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        devicetree@...r.kernel.org, Kishon Vijay Abraham I <kishon@...com>,
        Andy Shevchenko <andriy.shevchenko@...el.com>,
        cheol.yong.kim@...el.com, chuanhua.lei@...ux.intel.com,
        qi-ming.wu@...el.com, yixin.zhu@...el.com
Subject: Re: [PATCH v4 2/3] dt-bindings: phy: Add YAML schemas for Intel Combophy

On Tue, Mar 3, 2020 at 3:24 AM Dilip Kota <eswara.kota@...ux.intel.com> wrote:
>
>
> On 3/3/2020 9:50 AM, Rob Herring wrote:
> > On Mon, Mar 02, 2020 at 04:43:24PM +0800, Dilip Kota wrote:
> >> Combophy subsystem provides PHY support to various
> >> controllers, viz. PCIe, SATA and EMAC.
> >> Adding YAML schemas for the same.
> >>
> >> Signed-off-by: Dilip Kota <eswara.kota@...ux.intel.com>
> >> ---
> >> Changes on v4:
> >>    No changes.
> ...
> >> +additionalProperties: false
> >> +
> >> +examples:
> >> +  - |
> >> +    #include <dt-bindings/phy/phy-intel-combophy.h>
> >> +    combophy@...00000 {
> >> +        compatible = "intel,combophy-lgm", "intel,combo-phy";
> >> +        clocks = <&cgu0 1>;
> >> +        reg = <0xd0a00000 0x40000>,
> >> +              <0xd0a40000 0x1000>;
> >> +        reg-names = "core", "app";
> >> +        resets = <&rcu0 0x50 6>,
> >> +                 <&rcu0 0x50 17>;
> >> +        reset-names = "phy", "core";
> >> +        intel,syscfg = <&sysconf 0>;
> >> +        intel,hsio = <&hsiol 0>;
> >> +        intel,phy-mode = <COMBO_PHY_PCIE>;
> >> +
> >> +        phy@0 {
> > You need a 'reg' property to go with a unit-address.
> >
> > Really, I'd just simplify this to make parent 'resets' be 4 entries and
> > put '#phy-cells = <1>;' in the parent. Then you don't need these child
> > nodes.
> If child nodes are not present, use case like PCIe controller-0 using
> phy@0 and PCIe controller-1 using phy@1 wont be possible.

Yes, it will be.

For controller-0:
phys = <&phy 0>;

For controller-1:
phys = <&phy 1>;

Rob