enable prepare protect duty clock count count count rate accuracy phase cycle --------------------------------------------------------------------------------------------- xtal 11 11 0 24000000 0 0 50000 ffd1b000.pwm#mux1 0 0 0 24000000 0 0 50000 ffd1b000.pwm#mux0 1 1 0 24000000 0 0 50000 ff802000.pwm#mux1 1 1 0 24000000 0 0 50000 ff802000.pwm#mux0 0 0 0 24000000 0 0 50000 cts_oscin 0 0 0 24000000 0 0 50000 g12a_ao_cec_pre 0 0 0 24000000 0 0 50000 g12a_ao_cec_div 0 0 0 32742 0 0 50000 g12a_ao_cec_sel 0 0 0 32742 0 0 50000 g12a_ao_cec 0 0 0 32742 0 0 50000 g12a_ao_32k_by_oscin_pre 0 0 0 24000000 0 0 50000 g12a_ao_32k_by_oscin_sel 0 0 0 24000000 0 0 50000 g12a_ao_32k_by_oscin 0 0 0 24000000 0 0 50000 g12a_ao_cts_rtc_oscin 0 0 0 24000000 0 0 50000 g12a_ao_32k_by_oscin_div 0 0 0 32742 0 0 50000 g12a_ao_saradc_mux 0 0 0 24000000 0 0 50000 g12a_ao_saradc_div 0 0 0 150000 0 0 50000 g12a_ao_saradc_gate 0 0 0 150000 0 0 50000 cpub_clk_dyn0_sel 0 0 0 24000000 0 0 50000 cpub_clk_dyn0 0 0 0 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cts_vdac_sel 0 0 0 64899999 0 0 50000 cts_vdac 0 0 0 64899999 0 0 50000 cts_encp_sel 0 0 0 64899999 0 0 50000 cts_encp 0 0 0 64899999 0 0 50000 cts_enci_sel 0 0 0 64899999 0 0 50000 cts_enci 0 0 0 64899999 0 0 50000 vclk_div12_en 0 0 0 64899999 0 0 50000 vclk_div12 0 0 0 5408333 0 0 50000 vclk_div6_en 0 0 0 64899999 0 0 50000 vclk_div6 0 0 0 10816666 0 0 50000 vclk_div4_en 0 0 0 64899999 0 0 50000 vclk_div4 0 0 0 16224999 0 0 50000 vclk_div2_en 0 0 0 64899999 0 0 50000 vclk_div2 0 0 0 32449999 0 0 50000 hifi_pll_dco 0 0 0 0 0 0 50000 hifi_pll 0 0 0 0 0 0 50000 gp0_pll_dco 0 0 0 0 0 0 50000 gp0_pll 0 0 0 0 0 0 50000 sys_pll_dco 1 1 0 4800000000 0 0 50000 sys_pll 0 0 0 1200000000 0 0 50000 sys_pll_div16_en 0 0 0 1200000000 0 0 50000 sys_pll_div16 0 0 0 75000000 0 0 50000 fixed_pll_dco 2 2 0 3999999939 0 0 50000 mpll_50m_div 1 1 0 49999999 0 0 50000 mpll_50m 1 1 0 49999999 0 0 50000 ff64c000.mdio-multiplexer#mux 1 1 0 49999999 0 0 50000 ff64c000.mdio-multiplexer#pll 1 1 0 499999990 0 0 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aud_tdmin_c_sclk_pre_en 0 0 0 264599 0 0 50000 aud_tdmin_c_sclk_post_en 0 0 0 264599 0 0 50000 aud_tdmin_c_sclk 0 0 0 264599 0 0 50000 aud_tdmin_b_sclk_sel 0 0 0 264599 0 0 50000 aud_tdmin_b_sclk_pre_en 0 0 0 264599 0 0 50000 aud_tdmin_b_sclk_post_en 0 0 0 264599 0 0 50000 aud_tdmin_b_sclk 0 0 0 264599 0 0 50000 aud_tdmin_a_sclk_sel 0 0 0 264599 0 0 50000 aud_tdmin_a_sclk_pre_en 0 0 0 264599 0 0 50000 aud_tdmin_a_sclk_post_en 0 0 0 264599 0 0 50000 aud_tdmin_a_sclk 0 0 0 264599 0 0 50000 mpll1_div 0 0 0 393212849 0 0 50000 mpll1 0 0 0 393212849 0 0 50000 mpll2_div 0 0 0 294909637 0 0 50000 mpll2 0 0 0 294909637 0 0 50000 mpll3_div 0 0 0 0 0 0 50000 mpll3 0 0 0 0 0 0 50000 fclk_div2p5_div 0 0 0 799999987 0 0 50000 fclk_div2p5 0 0 0 799999987 0 0 50000 vdec_hevcf_sel 0 0 0 799999987 0 0 50000 vdec_hevcf_div 0 0 0 799999987 0 0 50000 vdec_hevcf 0 0 0 799999987 0 0 50000 vdec_hevc_sel 0 0 0 799999987 0 0 50000 vdec_hevc_div 0 0 0 799999987 0 0 50000 vdec_hevc 0 0 0 799999987 0 0 50000 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