[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CANAwSgS11Bo=KhbspY1w=8qpSjjN8ed81s71zBB9AGczBe=wTA@mail.gmail.com>
Date: Wed, 4 Mar 2020 23:23:33 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Linux USB Mailing List <linux-usb@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Felipe Balbi <balbi@...nel.org>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
linux-samsung-soc@...r.kernel.org,
Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCHv2 0/3] Add support for suspend clk for Exynos5422 SoC
Hi Krzysztof,
On Wed, 4 Mar 2020 at 13:41, Krzysztof Kozlowski <krzk@...nel.org> wrote:
>
> On Sun, Mar 01, 2020 at 09:20:15PM +0000, Anand Moon wrote:
> > Seried build and tested on linux next-20200228.
> >
> > This patch series tries to enable suspend clk using
> > exynos dwc3 driver, for this I have added new
> > compatible string "samsung,exynos5420-dwusb3"
> > so that we could add new suspend clk in addition
> > to the core clk. exynos dwc3 driver will help
> > enable/disable these clk.
>
> That's not entirely correct. You enable there SCLK which is a "special
> clock", not a "suspend clock". You use word "suspend: in multiple places
> in commits making an impression that it is about some suspend clock...
> no, there is no suspend clock.
>
Ok
> There is however a clock which driver calls suspend_clk (but it is just
> some name) and it is being enabled for entire lifetime of device (so
> also during suspend). AFAIU, this is not needed for Exynos5422 but I am
> not sure. So please convince me...
>
Yep you are absolutely correct. Yes all the CLK_SLK* are call special clk's
Earlier I had share the FSYS clk diagram for Exynos5422
[0] https://imgur.com/gallery/zAiBoyh
from the diagram I mapped the naming terminology.
CLKMUX_USBDRD300 --->CLKDIV_USBDRD300 ---> SCLK_USBDRD300 (48 MHz)
---> USBDRD30_0 (SUSPEND_CLK)
|
|--->CLKDIV_USBPHY300--->
SCLK_USBPHY300 (48 MHZ) ---> USBDRD30_PHY_0 (USB30_SCLK_100M |
USB20_PICO_CLKCORE)
CLKMUX_USBDRD301 --->CLKDIV_USBDRD301 ---> SCLK_USBDRD301 (48 MHz)
---> USBDRD30_1 (SUSPEND_CLK)
|
|--->CLKDIV_USBPHY301--->
SCLK_USBPHY301 (48 MHZ) ---> USBDRD30_PHY_1 (USB30_SCLK_100M)
SCLK_USBDRD300 USBDRD30_0 operating clock to 24 MHz
SCLK_USBDRD301 USBDRD30_PHY_0 operating clock to 24 MHz
SCLK_USBPHY300 USBPHY30_0 operating clock to 24 MHz
SCLK_USBPHY301 USBDRD30_PHY_1 operating clock to 24 Mhz
> However I have still the same questions:
> 1. What problem are you trying to solve here?
> 2. Why this is needed?
I am trying to get the USB clk to get enabled for FSYS power domain
to working efficiently.
> 3. What is fixed with this patch?
Currently locally I tried to enable the FSYS power domain for USB 3.0 / USB 2.0.
but it's not working as expected, need future study.
*Note:* For now plz discard these patches.
When I get the FSYS power domain to work correctly.
I will link with those patch which will be better for testing.
-Anand
>
> Best regards,
> Krzysztof
>
Powered by blists - more mailing lists