[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <1583431025-19802-1-git-send-email-luwei.kang@intel.com>
Date: Fri, 6 Mar 2020 01:56:54 +0800
From: Luwei Kang <luwei.kang@...el.com>
To: x86@...nel.org, linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Cc: peterz@...radead.org, mingo@...hat.com, acme@...nel.org,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
jolsa@...hat.com, namhyung@...nel.org, tglx@...utronix.de,
bp@...en8.de, hpa@...or.com, pbonzini@...hat.com,
sean.j.christopherson@...el.com, vkuznets@...hat.com,
wanpengli@...cent.com, jmattson@...gle.com, joro@...tes.org,
pawan.kumar.gupta@...ux.intel.com, ak@...ux.intel.com,
thomas.lendacky@....com, fenghua.yu@...el.com,
kan.liang@...ux.intel.com, like.xu@...ux.intel.com,
Luwei Kang <luwei.kang@...el.com>
Subject: [PATCH v1 00/11] PEBS virtualization enabling via DS
The Processor Event-Based Sampling(PEBS) supported on mainstream Intel
platforms can provide an architectural state of the instruction executed
after the instruction that caused the event. This patchset is going to
enable PEBS feature via DS on KVM for the Icelake server.
Although PEBS via DS supports EPT violations feature is supported starting
Skylake Server, but we have to pin DS area to avoid losing PEBS records due
to some issues.
BTW:
The PEBS virtualization via Intel PT patchset V1 has been posted out and the
later version will base on this patchset.
https://lkml.kernel.org/r/1572217877-26484-1-git-send-email-luwei.kang@intel.com/
Testing:
The guest can use PEBS feature like native. e.g.
# perf record -e instructions:ppp ./br_instr a
perf report on guest:
# Samples: 2K of event 'instructions:ppp', # Event count (approx.): 1473377250
# Overhead Command Shared Object Symbol
57.74% br_instr br_instr [.] lfsr_cond
41.40% br_instr br_instr [.] cmp_end
0.21% br_instr [kernel.kallsyms] [k] __lock_acquire
perf report on host:
# Samples: 2K of event 'instructions:ppp', # Event count (approx.): 1462721386
# Overhead Command Shared Object Symbol
57.90% br_instr br_instr [.] lfsr_cond
41.95% br_instr br_instr [.] cmp_end
0.05% br_instr [kernel.vmlinux] [k] lock_acquire
Kan Liang (4):
perf/x86/core: Support KVM to assign a dedicated counter for guest
PEBS
perf/x86/ds: Handle guest PEBS events overflow and inject fake PMI
perf/x86: Expose a function to disable auto-reload
KVM: x86/pmu: Decouple event enablement from event creation
Like Xu (1):
KVM: x86/pmu: Add support to reprogram PEBS event for guest counters
Luwei Kang (6):
KVM: x86/pmu: Implement is_pebs_via_ds_supported pmu ops
KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64
KVM: x86/pmu: PEBS MSRs emulation
KVM: x86/pmu: Expose PEBS feature to guest
KVM: x86/pmu: Introduce the mask value for fixed counter
KVM: x86/pmu: Adaptive PEBS virtualization enabling
arch/x86/events/intel/core.c | 74 +++++++++++++++++++++-
arch/x86/events/intel/ds.c | 59 ++++++++++++++++++
arch/x86/events/perf_event.h | 1 +
arch/x86/include/asm/kvm_host.h | 12 ++++
arch/x86/include/asm/msr-index.h | 4 ++
arch/x86/include/asm/perf_event.h | 2 +
arch/x86/kvm/cpuid.c | 9 ++-
arch/x86/kvm/pmu.c | 71 ++++++++++++++++++++-
arch/x86/kvm/pmu.h | 2 +
arch/x86/kvm/svm.c | 12 ++++
arch/x86/kvm/vmx/capabilities.h | 17 +++++
arch/x86/kvm/vmx/pmu_intel.c | 128 +++++++++++++++++++++++++++++++++++++-
arch/x86/kvm/vmx/vmx.c | 6 +-
arch/x86/kvm/vmx/vmx.h | 4 ++
arch/x86/kvm/x86.c | 19 +++++-
include/linux/perf_event.h | 2 +
kernel/events/core.c | 1 +
17 files changed, 414 insertions(+), 9 deletions(-)
--
1.8.3.1
Powered by blists - more mailing lists