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Date: Fri, 6 Mar 2020 23:29:27 +0100 From: Paul Cercueil <paul@...pouillou.net> To: Liam Girdwood <lgirdwood@...il.com>, Mark Brown <broonie@...nel.org>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Jaroslav Kysela <perex@...ex.cz>, Takashi Iwai <tiwai@...e.com> Cc: alsa-devel@...a-project.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, od@...c.me, Zhou Yanjie <zhouyanjie@...yeetech.com>, Paul Cercueil <paul@...pouillou.net>, stable@...r.kernel.org Subject: [PATCH 2/6] ASoC: jz4740-i2s: Fix divider written at incorrect offset in register The 4-bit divider value was written at offset 8, while the jz4740 programming manual locates it at offset 0. Fixes: 26b0aad80a86 ("ASoC: jz4740: Add dynamic sampling rate support to jz4740-i2s") Cc: stable@...r.kernel.org Signed-off-by: Paul Cercueil <paul@...pouillou.net> --- sound/soc/jz4740/jz4740-i2s.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/jz4740/jz4740-i2s.c b/sound/soc/jz4740/jz4740-i2s.c index 9d5405881209..434737b2b2b2 100644 --- a/sound/soc/jz4740/jz4740-i2s.c +++ b/sound/soc/jz4740/jz4740-i2s.c @@ -83,7 +83,7 @@ #define JZ_AIC_I2S_STATUS_BUSY BIT(2) #define JZ_AIC_CLK_DIV_MASK 0xf -#define I2SDIV_DV_SHIFT 8 +#define I2SDIV_DV_SHIFT 0 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT) #define I2SDIV_IDV_SHIFT 8 #define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT) -- 2.25.1
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