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Date:   Fri, 6 Mar 2020 17:08:03 -0800
To:     Nishanth Menon <>
Cc:     Arnd Bergmann <>, Tero Kristo <>,
        Linux ARM <>,
        Michal Hocko <>,
        Rik van Riel <>,
        Catalin Marinas <>,
        Santosh Shilimkar <>,
        Dave Chinner <>,
        Russell King - ARM Linux admin <>,
        Linux Kernel Mailing List <>,
        Linux-MM <>,
        Yafang Shao <>,
        Al Viro <>,
        Johannes Weiner <>,
        linux-fsdevel <>,, Kishon Vijay Abraham I <>,
        Linus Torvalds <>,
        Andrew Morton <>,
        Roman Gushchin <>
Subject: Re: [PATCH] vfs: keep inodes with page cache off the inode shrinker

On 3/6/20 12:34 PM, Nishanth Menon wrote:
> On 13:11-20200226, wrote:
>> +Nishant, Tero
>> On 2/26/20 1:01 PM, Arnd Bergmann wrote:
>>> On Wed, Feb 26, 2020 at 7:04 PM <> wrote:
>>>> On 2/13/20 8:52 AM, Arnd Bergmann wrote:
>>>>> On Wed, Feb 12, 2020 at 9:50 AM Russell King - ARM Linux admin
>>>>> <> wrote:
>>>> The Keystone generations of SOCs have been used in different areas and
>>>> they will be used for long unless says otherwise.
>>>> Apart from just split of lowmem and highmem, one of the peculiar thing
>>>> with Keystome family of SOCs is the DDR is addressable from two
>>>> addressing ranges. The lowmem address range is actually non-cached
>>>> range and the higher range is the cacheable.
>>> I'm aware of Keystone's special physical memory layout, but for the
>>> discussion here, this is actually irrelevant for the discussion about
>>> highmem here, which is only about the way we map all or part of the
>>> available physical memory into the 4GB of virtual address space.
>>> The far more important question is how much memory any users
>>> (in particular the subset that are going to update their kernels
>>> several years from now) actually have installed. Keystone-II is
>>> one of the rare 32-bit chips with fairly wide memory interfaces,
>>> having two 72-bit (with ECC) channels rather than the usual one
>>>    or two channels of 32-bit DDR3. This means a relatively cheap
>>> 4GB configuration using eight 256Mx16 chips is possible, or
>>> even a 8GB using sixteen or eighteen 512Mx8.
>>> Do you have an estimate on how common these 4GB and 8GB
>>> configurations are in practice outside of the TI evaluation
>>> board?
>>  From my TI memories, many K2 customers were going to install
>> more than 2G memory. Don't remember 8G, but 4G was the dominant
>> one afair. Will let Nishant/Tero elaborate latest on this.
> Thanks for the headsup, it took a little to dig up the current
> situation:
> ~few 1000s still relevant spread between 4G and 8G (confirmed that both
> are present, relevant and in use).
> I wish we could sunset, but unfortunately, I am told(and agree)
> that we should'nt just leave products (and these are long term
> products stuck in critical parts in our world) hanging in the air, and
> migrations to newer kernel do still take place periodically (the best
> I can talk in public forum at least).
Thanks Nishant !!

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