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Message-Id: <20200308163230.4002-5-afaerber@suse.de>
Date: Sun, 8 Mar 2020 17:32:22 +0100
From: Andreas Färber <afaerber@...e.de>
To: linux-arm-kernel@...ts.infradead.org
Cc: Wells Lu 呂芳騰
<wells.lu@...plus.com>, Dvorkin Dmitry <dvorkin@...bo.com>,
linux-kernel@...r.kernel.org,
Andreas Färber <afaerber@...e.de>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org
Subject: [RFC 04/11] dt-bindings: interrupt-controller: Add Sunplus SP7021 mux
The Sunplus SP7021 SoC has an interrupt mux.
Cc: Wells Lu 呂芳騰 <wells.lu@...plus.com>
Signed-off-by: Andreas Färber <afaerber@...e.de>
---
.../sunplus,pentagram-intc.yaml | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
new file mode 100644
index 000000000000..baaf7bcd4a71
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/sunplus,pentagram-intc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sunplus,pentagram-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus Pentagram SoC Interrupt Controller
+
+maintainers:
+ - Andreas Färber <afaerber@...e.de>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: sunplus,sp7021-intc
+
+ reg:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 2
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ interrupt-controller@...00780 {
+ compatible = "sunplus,sp7021-intc";
+ reg = <0x9c000780 0x80>,
+ <0x9c000a80 0x80>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+...
--
2.16.4
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