linux-kernel - Re: [PATCH v4 1/7] dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <1583740539.3995.15.camel@mtksdaap41>
Date:   Mon, 9 Mar 2020 15:55:39 +0800
From:   Nick Fan <nick.fan@...iatek.com>
To:     Steven Price <steven.price@....com>
CC:     Rob Herring <robh@...nel.org>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Sj Huang <sj.huang@...iatek.com>,
        David Airlie <airlied@...ux.ie>,
        "Daniel Vetter" <daniel@...ll.ch>,
        Mark Rutland <Mark.Rutland@....com>,
        "Matthias Brugger" <matthias.bgg@...il.com>,
        Tomeu Vizoso <tomeu.vizoso@...labora.com>,
        Alyssa Rosenzweig <alyssa.rosenzweig@...labora.com>,
        Liam Girdwood <lgirdwood@...il.com>,
        Mark Brown <broonie@...nel.org>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        Devicetree List <devicetree@...r.kernel.org>,
        lkml <linux-kernel@...r.kernel.org>,
        linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        Hsin-Yi Wang <hsinyi@...omium.org>,
        Ulf Hansson <ulf.hansson@...aro.org>
Subject: Re: [PATCH v4 1/7] dt-bindings: gpu: mali-bifrost: Add Mediatek
 MT8183

On Fri, 2020-03-06 at 14:43 +0000, Steven Price wrote:
> On Fri, Mar 06, 2020 at 02:13:08PM +0000, Rob Herring wrote:
> > On Thu, Mar 5, 2020 at 8:34 PM Nick Fan <nick.fan@...iatek.com> wrote:
> > >
> > > Sorry for my late reply.
> > > I have checked internally.
> > > The MT8183_POWER_DOMAIN_MFG_2D is just a legacy name, not really 2D
> > > domain.
> > >
> > > If the naming too confusing, we can change this name to
> > > MT8183_POWER_DOMAIN_MFG_CORE2 for consistency.
> > 
> > Can you clarify what's in each domain? Are there actually 3 shader
> > cores (IIRC, that should be discoverable)?
> 
> The cover letter from Nicolas includes:
> 
> > [  501.321752] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
> 
> 0x7 is three bits set, so it certainly looks like there are 3 shader
> cores. Of course I wouldn't guarantee that it is as simple as each power
> domain has a shader core in. The job manager and tiler also need to be
> powered somehow, so they are either sharing with a shader core or
> there's something more complex going on.
> 
> Steve
> 
There are actually five power domains in total for MT8183 GPU.

There are 3 shader cores in MT8183.

They can be listed as following for each power domain:
1.MT8183_POWER_DOMAIN_MFG_ASYNC : SOC bus logic
2.MT8183_POWER_DOMAIN_MFG : GPU job manager & tiler
3.MT8183_POWER_DOMAIN_MFG_CORE0 : GPU shader core 0
4.MT8183_POWER_DOMAIN_MFG_CORE1 : GPU shader core 1
5.MT8183_POWER_DOMAIN_MFG_2D : GPU shader core 2

There are other power domain dependency can be reference in the
following link.
https://lkml.org/lkml/2019/2/1/166

You can check the power domain dependencies as following
==========================================================
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+	{MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+	{MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+	{MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+	{MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
==========================================================

Thanks

Nick Fan