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Message-ID: <CAAhSdy0tNAX-XV9-rh+pDLV-MXQ+v1trMFp6Vq_a6yD3HecPyQ@mail.gmail.com>
Date: Mon, 9 Mar 2020 17:28:19 +0530
From: Anup Patel <anup@...infault.org>
To: Anup Patel <anup.patel@....com>
Cc: Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Atish Patra <atish.patra@....com>,
Alistair Francis <Alistair.Francis@....com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
Marc Zyngier <maz@...nel.org>
Subject: Re: [PATCH v4 1/5] RISC-V: self-contained IPI handling routine
Fixed Marc's email address.
On Mon, Mar 9, 2020 at 4:32 PM Anup Patel <anup.patel@....com> wrote:
>
> Currently, the IPI handling routine riscv_software_interrupt() does
> not take any argument and also does not perform irq_enter()/irq_exit().
>
> This patch makes IPI handling routine more self-contained by:
> 1. Passing "pt_regs *" argument
> 2. Explicitly doing irq_enter()/irq_exit()
> 3. Explicitly save/restore "pt_regs *" using set_irq_regs()
>
> With above changes, IPI handling routine does not depend on caller
> function to perform irq_enter()/irq_exit() and save/restore of
> "pt_regs *" hence its more self-contained. This also enables us
> to call IPI handling routine from IRQCHIP drivers.
>
> Signed-off-by: Anup Patel <anup.patel@....com>
> ---
> arch/riscv/include/asm/irq.h | 1 -
> arch/riscv/include/asm/smp.h | 3 +++
> arch/riscv/kernel/irq.c | 16 ++++++++++------
> arch/riscv/kernel/smp.c | 11 +++++++++--
> 4 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h
> index 6e1b0e0325eb..0183e15ace66 100644
> --- a/arch/riscv/include/asm/irq.h
> +++ b/arch/riscv/include/asm/irq.h
> @@ -13,7 +13,6 @@
> #define NR_IRQS 0
>
> void riscv_timer_interrupt(void);
> -void riscv_software_interrupt(void);
>
> #include <asm-generic/irq.h>
>
> diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h
> index f4c7cfda6b7f..40bb1c15a731 100644
> --- a/arch/riscv/include/asm/smp.h
> +++ b/arch/riscv/include/asm/smp.h
> @@ -28,6 +28,9 @@ void show_ipi_stats(struct seq_file *p, int prec);
> /* SMP initialization hook for setup_arch */
> void __init setup_smp(void);
>
> +/* Called from C code, this handles an IPI. */
> +void handle_IPI(struct pt_regs *regs);
> +
> /* Hook for the generic smp_call_function_many() routine. */
> void arch_send_call_function_ipi_mask(struct cpumask *mask);
>
> diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
> index 345c4f2eba13..bb0bfcd537e7 100644
> --- a/arch/riscv/kernel/irq.c
> +++ b/arch/riscv/kernel/irq.c
> @@ -19,12 +19,15 @@ int arch_show_interrupts(struct seq_file *p, int prec)
>
> asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
> {
> - struct pt_regs *old_regs = set_irq_regs(regs);
> + struct pt_regs *old_regs;
>
> - irq_enter();
> switch (regs->cause & ~CAUSE_IRQ_FLAG) {
> case RV_IRQ_TIMER:
> + old_regs = set_irq_regs(regs);
> + irq_enter();
> riscv_timer_interrupt();
> + irq_exit();
> + set_irq_regs(old_regs);
> break;
> #ifdef CONFIG_SMP
> case RV_IRQ_SOFT:
> @@ -32,19 +35,20 @@ asmlinkage __visible void __irq_entry do_IRQ(struct pt_regs *regs)
> * We only use software interrupts to pass IPIs, so if a non-SMP
> * system gets one, then we don't know what to do.
> */
> - riscv_software_interrupt();
> + handle_IPI(regs);
> break;
> #endif
> case RV_IRQ_EXT:
> + old_regs = set_irq_regs(regs);
> + irq_enter();
> handle_arch_irq(regs);
> + irq_exit();
> + set_irq_regs(old_regs);
> break;
> default:
> pr_alert("unexpected interrupt cause 0x%lx", regs->cause);
> BUG();
> }
> - irq_exit();
> -
> - set_irq_regs(old_regs);
> }
>
> void __init init_IRQ(void)
> diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
> index eb878abcaaf8..1e8f44a47e14 100644
> --- a/arch/riscv/kernel/smp.c
> +++ b/arch/riscv/kernel/smp.c
> @@ -121,11 +121,14 @@ static inline void clear_ipi(void)
> clint_clear_ipi(cpuid_to_hartid_map(smp_processor_id()));
> }
>
> -void riscv_software_interrupt(void)
> +void handle_IPI(struct pt_regs *regs)
> {
> + struct pt_regs *old_regs = set_irq_regs(regs);
> unsigned long *pending_ipis = &ipi_data[smp_processor_id()].bits;
> unsigned long *stats = ipi_data[smp_processor_id()].stats;
>
> + irq_enter();
> +
> clear_ipi();
>
> while (true) {
> @@ -136,7 +139,7 @@ void riscv_software_interrupt(void)
>
> ops = xchg(pending_ipis, 0);
> if (ops == 0)
> - return;
> + goto done;
>
> if (ops & (1 << IPI_RESCHEDULE)) {
> stats[IPI_RESCHEDULE]++;
> @@ -158,6 +161,10 @@ void riscv_software_interrupt(void)
> /* Order data access and bit testing. */
> mb();
> }
> +
> +done:
> + irq_exit();
> + set_irq_regs(old_regs);
> }
>
> static const char * const ipi_names[] = {
> --
> 2.17.1
>
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