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Message-ID: <20200309142529.GB13343@arm.com>
Date: Mon, 9 Mar 2020 14:25:29 +0000
From: Ionela Voinescu <ionela.voinescu@....com>
To: Marc Zyngier <maz@...nel.org>
Cc: catalin.marinas@....com, will@...nel.org, mark.rutland@....com,
suzuki.poulose@....com, sudeep.holla@....com, lukasz.luba@....com,
valentin.schneider@....com, dietmar.eggemann@....com,
rjw@...ysocki.net, pkondeti@...eaurora.org, peterz@...radead.org,
mingo@...hat.com, vincent.guittot@...aro.org,
viresh.kumar@...aro.org, linux-arm-kernel@...ts.infradead.org,
linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, James Morse <james.morse@....com>,
Julien Thierry <julien.thierry.kdev@...il.com>
Subject: Re: [PATCH v5 3/7] arm64/kvm: disable access to AMU registers from
kvm guests
Hi Marc,
On Thursday 27 Feb 2020 at 19:58:32 (+0000), Marc Zyngier wrote:
[..]
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index 3e909b117f0c..44354c812783 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -1003,6 +1003,20 @@ static bool access_pmuserenr(struct kvm_vcpu
> > *vcpu, struct sys_reg_params *p,
> > { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
> > access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
> >
> > +static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> > + const struct sys_reg_desc *r)
> > +{
> > + kvm_inject_undefined(vcpu);
> > +
> > + return false;
> > +}
> > +
> > +/* Macro to expand the AMU counter and type registers*/
> > +#define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)),
> > access_amu }
> > +#define AMU_AMEVTYPE0_EL0(n) { SYS_DESC(SYS_AMEVTYPE0_EL0(n)),
> > access_amu }
> > +#define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)),
> > access_amu }
> > +#define AMU_AMEVTYPE1_EL0(n) { SYS_DESC(SYS_AMEVTYPE1_EL0(n)),
> > access_amu }
> > +
> > static bool trap_ptrauth(struct kvm_vcpu *vcpu,
> > struct sys_reg_params *p,
> > const struct sys_reg_desc *rd)
> > @@ -1078,8 +1092,10 @@ static u64 read_id_reg(const struct kvm_vcpu
> > *vcpu,
> > (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
> > u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
> >
> > - if (id == SYS_ID_AA64PFR0_EL1 && !vcpu_has_sve(vcpu)) {
> > - val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
> > + if (id == SYS_ID_AA64PFR0_EL1) {
> > + if (!vcpu_has_sve(vcpu))
> > + val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
> > + val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
>
> This will definitely conflict with some of the ongoing rework I have[1].
> I'm happy to provide this as a stable branch for you to rebase on top,
> or use an arm64 provided branch to rebase my stoff on top.
>
> Just let me know how you want to proceed.
>
Catalin added the AMU patches on top of 5.6-rc3 at [1].
Is this okay as a base branch for your patches?
Thanks,
Ionela.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/amu
> Thanks,
>
> M.
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/commit/?h=kvm-arm64/debug-fixes-5.6&id=454fb7398d3626328f7f771c07d21e894e4e1a3b
> --
> Jazz is not dead. It just smells funny...
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