linux-kernel - Re: [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum when reading GICD

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Date:   Tue, 10 Mar 2020 13:34:59 +0100
From:   Robert Richter <rrichter@...vell.com>
To:     Marc Zyngier <maz@...nel.org>
CC:     <kvmarm@...ts.cs.columbia.edu>, <linux-kernel@...r.kernel.org>,
        Eric Auger <eric.auger@...hat.com>,
        James Morse <james.morse@....com>,
        Julien Thierry <julien.thierry.kdev@...il.com>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Andrew Murray <Andrew.Murray@....com>,
        Zenghui Yu <yuzenghui@...wei.com>
Subject: Re: [PATCH v3 03/32] irqchip/gic-v3: Workaround Cavium TX1 erratum
 when reading GICD_TYPER2

On 10.03.20 11:41:09, Marc Zyngier wrote:
> On 2020-03-09 22:11, Robert Richter wrote:
> > On 24.12.19 11:10:26, Marc Zyngier wrote:

> > > @@ -1502,6 +1512,12 @@ static const struct gic_quirk gic_quirks[] = {
> > >  		.mask	= 0xffffffff,
> > >  		.init	= gic_enable_quirk_hip06_07,
> > >  	},
> > > +	{
> > > +		.desc	= "GICv3: Cavium TX1 GICD_TYPER2 erratum",
> > 
> > There is no errata number yet.
> 
> Please let me know when/if you obtain one.

Yes, will do.

> 
> > 
> > > +		.iidr	= 0xa100034c,
> > > +		.mask	= 0xfff00fff,
> > > +		.init	= gic_enable_quirk_tx1,
> > 
> > All TX1 and OcteonTX parts are affected, which is a0-a7 and b0-b7. So
> > the iidr/mask should be:
> > 
> > 		.iidr   = 0xa000034c,
> > 		.mask   = 0xe8f00fff,
> 
> Thanks, that's pretty helpful. I'll update the patch with these values
> and the corresponding description.

Thanks for the update.

> 
> > > +	},
> > >  	{
> > >  	}
> > >  };
> > > @@ -1577,7 +1593,12 @@ static int __init gic_init_bases(void __iomem
> > > *dist_base,
> > >  	pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32);
> > >  	pr_info("%d Extended SPIs implemented\n", GIC_ESPI_NR);
> > > 
> > > -	gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base +
> > > GICD_TYPER2);
> > > +	/*
> > > +	 * ThunderX1 explodes on reading GICD_TYPER2, in total violation
> > > +	 * of the spec (which says that reserved addresses are RES0).
> > > +	 */
> > > +	if (!(gic_data.flags & FLAGS_WORKAROUND_GICD_TYPER2_TX1))
> > > +		gic_data.rdists.gicd_typer2 = readl_relaxed(gic_data.dist_base +
> > > GICD_TYPER2);
> > 
> > You already said that checking for ArchRev of GICD_PIDR2 isn't an
> > option here. Though, it could...
> 
> Once GICv3.2 starts using this register as well (because GICD_TYPER is
> already completely full), we'd have to fix it again. There is also the thing
> you hinted at in the other thread: TX1 will generate a SEA on every reserved
> GICD registers, so we may need to protect more than just this one over time,
> and maybe more than just in the distributor.

I am fine with both. And right, it would be possibly needed for other
ranges too.

Thanks,

-Robert

> 
> Thanks,
> 
>         M.
> -- 
> Jazz is not dead. It just smells funny...