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Date: Wed, 11 Mar 2020 19:26:02 +0000 From: Mark Brown <broonie@...nel.org> To: Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org> Cc: Alexander Viro <viro@...iv.linux.org.uk>, Paul Elliott <paul.elliott@....com>, Peter Zijlstra <peterz@...radead.org>, Yu-cheng Yu <yu-cheng.yu@...el.com>, Amit Kachhap <amit.kachhap@....com>, Vincenzo Frascino <vincenzo.frascino@....com>, Marc Zyngier <maz@...nel.org>, Eugene Syromiatnikov <esyr@...hat.com>, Szabolcs Nagy <szabolcs.nagy@....com>, "H . J . Lu " <hjl.tools@...il.com>, Andrew Jones <drjones@...hat.com>, Kees Cook <keescook@...omium.org>, Arnd Bergmann <arnd@...db.de>, Jann Horn <jannh@...gle.com>, Richard Henderson <richard.henderson@...aro.org>, Kristina Martšenko <kristina.martsenko@....com>, Thomas Gleixner <tglx@...utronix.de>, Florian Weimer <fweimer@...hat.com>, Sudakshina Das <sudi.das@....com>, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org, linux-fsdevel@...r.kernel.org, Dave Martin <Dave.Martin@....com>, Mark Rutland <mark.rutland@....com>, Mark Brown <broonie@...nel.org> Subject: [PATCH v9 07/13] arm64: unify native/compat instruction skipping From: Dave Martin <Dave.Martin@....com> Skipping of an instruction on AArch32 works a bit differently from AArch64, mainly due to the different CPSR/PSTATE semantics. Currently arm64_skip_faulting_instruction() is only suitable for AArch64, and arm64_compat_skip_faulting_instruction() handles the IT state machine but is local to traps.c. Since manual instruction skipping implies a trap, it's a relatively slow path. So, make arm64_skip_faulting_instruction() handle both compat and native, and get rid of the arm64_compat_skip_faulting_instruction() special case. Signed-off-by: Dave Martin <Dave.Martin@....com> Reviewed-by: Mark Rutland <mark.rutland@....com> Reviewed-by: Kees Cook <keescook@...omium.org> Signed-off-by: Mark Brown <broonie@...nel.org> --- arch/arm64/kernel/traps.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index b8c714dda851..bc9f4292bfc3 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -272,6 +272,8 @@ void arm64_notify_die(const char *str, struct pt_regs *regs, } } +static void advance_itstate(struct pt_regs *regs); + void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) { regs->pc += size; @@ -282,6 +284,9 @@ void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) */ if (user_mode(regs)) user_fastforward_single_step(current); + + if (regs->pstate & PSR_MODE32_BIT) + advance_itstate(regs); } static LIST_HEAD(undef_hook); @@ -644,19 +649,12 @@ static void advance_itstate(struct pt_regs *regs) compat_set_it_state(regs, it); } -static void arm64_compat_skip_faulting_instruction(struct pt_regs *regs, - unsigned int sz) -{ - advance_itstate(regs); - arm64_skip_faulting_instruction(regs, sz); -} - static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) { int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; pt_regs_write_reg(regs, reg, arch_timer_get_rate()); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_32_hooks[] = { @@ -676,7 +674,7 @@ static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) pt_regs_write_reg(regs, rt, lower_32_bits(val)); pt_regs_write_reg(regs, rt2, upper_32_bits(val)); - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); } static const struct sys64_hook cp15_64_hooks[] = { @@ -697,7 +695,7 @@ void do_cp15instr(unsigned int esr, struct pt_regs *regs) * There is no T16 variant of a CP access, so we * always advance PC by 4 bytes. */ - arm64_compat_skip_faulting_instruction(regs, 4); + arm64_skip_faulting_instruction(regs, 4); return; } -- 2.20.1
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