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Message-ID: <73820857-a9dd-0e5e-c3ee-fd63f4e5f10b@loongson.cn>
Date: Wed, 11 Mar 2020 17:28:00 +0800
From: Tiezhu Yang <yangtiezhu@...ngson.cn>
To: Jiaxun Yang <jiaxun.yang@...goat.com>
Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Huacai Chen <chenhc@...ote.com>,
linux-mips <linux-mips@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Xuefeng Li <lixuefeng@...ngson.cn>
Subject: Re: 回复:[PATCH] MIPS: Loongson: Add model name to /proc/cpuinfo
On 03/11/2020 02:53 PM, Jiaxun Yang wrote:
>
> ---- 在 星期三, 2020-03-11 14:33:34 Tiezhu Yang <yangtiezhu@...ngson.cn> 撰写 ----
> > In the current code, when execute command "cat /proc/cpuinfo" or "lscpu",
> > it can not get cpu type and frequency directly because the model name is
> > not exist, so add it.
> >
> > E.g. without this patch:
> >
> > [loongson@...alhost ~]$ lscpu
> > Architecture: mips64
> > Byte Order: Little Endian
> > CPU(s): 4
> > On-line CPU(s) list: 0-3
> > Thread(s) per core: 1
> > Core(s) per socket: 4
> > Socket(s): 1
> > NUMA node(s): 1
> > L1d cache: 64K
> > L1i cache: 64K
> > L2 cache: 2048K
> > NUMA node0 CPU(s): 0-3
> >
> > With this patch:
> >
> > [loongson@...alhost ~]$ lscpu
> > Architecture: mips64
> > Byte Order: Little Endian
> > CPU(s): 4
> > On-line CPU(s) list: 0-3
> > Thread(s) per core: 1
> > Core(s) per socket: 4
> > Socket(s): 1
> > NUMA node(s): 1
> > Model name: Loongson-3A R3 (Loongson-3A3000) @ 1449MHz
> > L1d cache: 64K
> > L1i cache: 64K
> > L2 cache: 2048K
> > NUMA node0 CPU(s): 0-3
>
> Hi Tiezhu,
>
> Thanks for your patch, you're the successor of Huacai:
>
> https://www.linux-mips.org/archives/linux-mips/2018-09/msg00113.html
Hi Jiaxun,
Thanks for your notice.
>
> I think it's worthy to have this string in cpuinfo as many userspace
> program is parsing it beacuse x86 have it.
>
> See my review comments below:
>
> >
> > Signed-off-by: Tiezhu Yang <yangtiezhu@...ngson.cn>
> > ---
> > arch/mips/include/asm/cpu-info.h | 1 +
> > arch/mips/kernel/cpu-probe.c | 27 +++++++++++++++++++++++----
> > arch/mips/kernel/proc.c | 4 ++++
> > 3 files changed, 28 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
> > index ed7ffe4..50e924e 100644
> > --- a/arch/mips/include/asm/cpu-info.h
> > +++ b/arch/mips/include/asm/cpu-info.h
> > @@ -115,6 +115,7 @@ extern struct cpuinfo_mips cpu_data[];
> > extern void cpu_probe(void);
> > extern void cpu_report(void);
> >
> > +extern const char *__model_name[];
> > extern const char *__cpu_name[];
> > #define cpu_name_string() __cpu_name[raw_smp_processor_id()]
> >
> > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> > index 6ab6b03..3ae40cc 100644
> > --- a/arch/mips/kernel/cpu-probe.c
> > +++ b/arch/mips/kernel/cpu-probe.c
> > @@ -1548,6 +1548,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
> > set_elf_platform(cpu, "loongson2e");
> > set_isa(c, MIPS_CPU_ISA_III);
> > c->fpu_msk31 |= FPU_CSR_CONDX;
> > + __model_name[cpu] = "Loongson-2E";
> > break;
> > case PRID_REV_LOONGSON2F:
> > c->cputype = CPU_LOONGSON2EF;
> > @@ -1555,23 +1556,37 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
> > set_elf_platform(cpu, "loongson2f");
> > set_isa(c, MIPS_CPU_ISA_III);
> > c->fpu_msk31 |= FPU_CSR_CONDX;
> > + __model_name[cpu] = "Loongson-2F";
> > break;
> > case PRID_REV_LOONGSON3A_R1:
> > c->cputype = CPU_LOONGSON64;
> > __cpu_name[cpu] = "ICT Loongson-3";
> > set_elf_platform(cpu, "loongson3a");
> > set_isa(c, MIPS_CPU_ISA_M64R1);
> > - c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
> > - MIPS_ASE_LOONGSON_EXT);
> > + c->ases |= (MIPS_ASE_LOONGSON_MMI |
> > + MIPS_ASE_LOONGSON_CAM |
> > + MIPS_ASE_LOONGSON_EXT);
>
> Is the newline intentional?
> Also applied to code below.
Yes, just fix the checkpatch.pl warning:
WARNING: line over 80 characters
#78: FILE: arch/mips/kernel/cpu-probe.c:1575:
+ c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
>
> > + __model_name[cpu] = "Loongson-3A R1 (Loongson-3A1000)";
> > break;
> > case PRID_REV_LOONGSON3B_R1:
> > + c->cputype = CPU_LOONGSON64;
> > + __cpu_name[cpu] = "ICT Loongson-3";
> > + set_elf_platform(cpu, "loongson3b");
> > + set_isa(c, MIPS_CPU_ISA_M64R1);
> > + c->ases |= (MIPS_ASE_LOONGSON_MMI |
> > + MIPS_ASE_LOONGSON_CAM |
> > + MIPS_ASE_LOONGSON_EXT);
> > + __model_name[cpu] = "Loongson-3B R1 (Loongson-3B1000)";
> > + break;
> > case PRID_REV_LOONGSON3B_R2:
> > c->cputype = CPU_LOONGSON64;
> > __cpu_name[cpu] = "ICT Loongson-3";
> > set_elf_platform(cpu, "loongson3b");
> > set_isa(c, MIPS_CPU_ISA_M64R1);
> > - c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
> > - MIPS_ASE_LOONGSON_EXT);
> > + c->ases |= (MIPS_ASE_LOONGSON_MMI |
> > + MIPS_ASE_LOONGSON_CAM |
> > + MIPS_ASE_LOONGSON_EXT);
> > + __model_name[cpu] = "Loongson-3B R2 (Loongson-3B1500)";
> > break;
> > }
> >
> > @@ -1926,6 +1941,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
> > __cpu_name[cpu] = "ICT Loongson-3";
> > set_elf_platform(cpu, "loongson3a");
> > set_isa(c, MIPS_CPU_ISA_M64R2);
> > + __model_name[cpu] = "Loongson-3A R2 (Loongson-3A2000)";
> > break;
> > case PRID_REV_LOONGSON3A_R3_0:
> > case PRID_REV_LOONGSON3A_R3_1:
> > @@ -1933,6 +1949,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
> > __cpu_name[cpu] = "ICT Loongson-3";
> > set_elf_platform(cpu, "loongson3a");
> > set_isa(c, MIPS_CPU_ISA_M64R2);
> > + __model_name[cpu] = "Loongson-3A R3 (Loongson-3A3000)";
> > break;
> > }
> >
> > @@ -1952,6 +1969,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
> > c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> > c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
> > MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
> > + __model_name[cpu] = "Loongson-3A R4 (Loongson-3A4000)";
> > break;
> > default:
> > panic("Unknown Loongson Processor ID!");
> > @@ -2111,6 +2129,7 @@ u64 __ua_limit;
> > EXPORT_SYMBOL(__ua_limit);
> > #endif
> >
> > +const char *__model_name[NR_CPUS];
> > const char *__cpu_name[NR_CPUS];
> > const char *__elf_platform;
> >
> > diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
> > index f8d3671..5fc74e6 100644
> > --- a/arch/mips/kernel/proc.c
> > +++ b/arch/mips/kernel/proc.c
> > @@ -15,6 +15,7 @@
> > #include <asm/mipsregs.h>
> > #include <asm/processor.h>
> > #include <asm/prom.h>
> > +#include <asm/time.h>
> >
> > unsigned int vced_count, vcei_count;
> >
> > @@ -63,6 +64,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
> > seq_printf(m, fmt, __cpu_name[n],
> > (version >> 4) & 0x0f, version & 0x0f,
> > (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
> > + if (__model_name[n])
> > + seq_printf(m, "model name\t\t: %s @ %uMHz\n",
> > + __model_name[n], mips_hpt_frequency / 500000);
> > seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
>
> Actually I don't think take mips_hpt_frequency here is a good option. mips_hpt_frequency
> is used by cevt-r4k. Processors like Ingenic don't use cevt-r4k don't have it.
>
> Probably you can do as what Huacai did, append the frequency part in platform code.
OK, I will do it.
Thanks,
Tiezhu Yang
>
>> cpu_data[n].udelay_val / (500000/HZ),
> > (cpu_data[n].udelay_val / (5000/HZ)) % 100);
> > --
> > 2.1.0
> >
> >
>
> Thanks.
>
> --
> Jiaxun Yang
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