linux-kernel - RE: [PATCHv7] arm64: dts: ls1028a: Add PCIe controller DT nodes

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Message-ID: <DB8PR04MB674761BF8BA68ACA26497B4784FC0@DB8PR04MB6747.eurprd04.prod.outlook.com>
Date:   Wed, 11 Mar 2020 09:50:29 +0000
From:   "Z.q. Hou" <zhiqiang.hou@....com>
To:     Shawn Guo <shawnguo@...nel.org>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "michael@...le.cc" <michael@...le.cc>, Leo Li <leoyang.li@....com>,
        Mingkai Hu <mingkai.hu@....com>,
        "M.h. Lian" <minghuan.lian@....com>,
        Xiaowei Bao <xiaowei.bao@....com>
Subject: RE: [PATCHv7] arm64: dts: ls1028a: Add PCIe controller DT nodes

Hi Shawn,

Thanks a lot for your comments!

> -----Original Message-----
> From: Shawn Guo <shawnguo@...nel.org>
> Sent: 2020年3月11日 16:21
> To: Z.q. Hou <zhiqiang.hou@....com>
> Cc: devicetree@...r.kernel.org; linux-kernel@...r.kernel.org;
> robh+dt@...nel.org; michael@...le.cc; Leo Li <leoyang.li@....com>;
> Mingkai Hu <mingkai.hu@....com>; M.h. Lian <minghuan.lian@....com>;
> Xiaowei Bao <xiaowei.bao@....com>
> Subject: Re: [PATCHv7] arm64: dts: ls1028a: Add PCIe controller DT nodes
> 
> On Mon, Mar 02, 2020 at 12:23:05PM +0800, Zhiqiang Hou wrote:
> > From: Xiaowei Bao <xiaowei.bao@....com>
> >
> > LS1028a implements 2 PCIe 3.0 controllers.
> >
> > Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> > Tested-by: Michael Walle <michael@...le.cc>
> > ---
> > V7:
> >  - Rebased the patch to the latest code base.
> >  - Added property 'iommu-map'.
> >
> >  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 54
> +++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index 41c9633293fb..3f31641dcced 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -717,6 +717,60 @@
> >  			#thermal-sensor-cells = <1>;
> >  		};
> >
> > +		pcie@...0000 {
> 
> Please keep nodes sorted in unit-address.

OK, will correct in next version.

Thanks,
Zhiqiang

> 
> Shawn
> 
> > +			compatible = "fsl,ls1028a-pcie";
> > +			reg = <0x00 0x03400000 0x0 0x00100000   /* controller
> registers */
> > +			       0x80 0x00000000 0x0 0x00002000>; /* configuration
> space */
> > +			reg-names = "regs", "config";
> > +			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME
> interrupt */
> > +				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer
> interrupt */
> > +			interrupt-names = "pme", "aer";
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +			device_type = "pci";
> > +			dma-coherent;
> > +			num-viewport = <8>;
> > +			bus-range = <0x0 0xff>;
> > +			ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0
> 0x00010000   /* downstream I/O */
> > +				  0x82000000 0x0 0x40000000 0x80 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > +			msi-parent = <&its>;
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 7>;
> > +			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109
> IRQ_TYPE_LEVEL_HIGH>,
> > +					<0000 0 0 2 &gic 0 0 GIC_SPI 110
> IRQ_TYPE_LEVEL_HIGH>,
> > +					<0000 0 0 3 &gic 0 0 GIC_SPI 111
> IRQ_TYPE_LEVEL_HIGH>,
> > +					<0000 0 0 4 &gic 0 0 GIC_SPI 112
> IRQ_TYPE_LEVEL_HIGH>;
> > +			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> > +			status = "disabled";
> > +		};
> > +
> > +		pcie@...0000 {
> > +			compatible = "fsl,ls1028a-pcie";
> > +			reg = <0x00 0x03500000 0x0 0x00100000   /* controller
> registers */
> > +			       0x88 0x00000000 0x0 0x00002000>; /* configuration
> space */
> > +			reg-names = "regs", "config";
> > +			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> > +				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "pme", "aer";
> > +			#address-cells = <3>;
> > +			#size-cells = <2>;
> > +			device_type = "pci";
> > +			dma-coherent;
> > +			num-viewport = <8>;
> > +			bus-range = <0x0 0xff>;
> > +			ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0
> 0x00010000   /* downstream I/O */
> > +				  0x82000000 0x0 0x40000000 0x88 0x40000000 0x0
> 0x40000000>; /* non-prefetchable memory */
> > +			msi-parent = <&its>;
> > +			#interrupt-cells = <1>;
> > +			interrupt-map-mask = <0 0 0 7>;
> > +			interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114
> IRQ_TYPE_LEVEL_HIGH>,
> > +					<0000 0 0 2 &gic 0 0 GIC_SPI 115
> IRQ_TYPE_LEVEL_HIGH>,
> > +					<0000 0 0 3 &gic 0 0 GIC_SPI 116
> IRQ_TYPE_LEVEL_HIGH>,
> > +					<0000 0 0 4 &gic 0 0 GIC_SPI 117
> IRQ_TYPE_LEVEL_HIGH>;
> > +			iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
> > +			status = "disabled";
> > +		};
> > +
> >  		pcie@...000000 { /* Integrated Endpoint Root Complex */
> >  			compatible = "pci-host-ecam-generic";
> >  			reg = <0x01 0xf0000000 0x0 0x100000>;
> > --
> > 2.17.1
> >