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Message-ID: <3908561D78D1C84285E8C5FCA982C28F7F59AA85@ORSMSX115.amr.corp.intel.com>
Date:   Wed, 11 Mar 2020 16:05:07 +0000
From:   "Luck, Tony" <tony.luck@...el.com>
To:     Wei Huang <wei.huang2@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "bp@...e.de" <bp@...e.de>,
        "yazen.ghannam@....com" <yazen.ghannam@....com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "smita.koralahallichannabasappa@....com" 
        <smita.koralahallichannabasappa@....com>
Subject: RE: [PATCH 1/1] x86/mce/amd: Add PPIN support for AMD MCE

+		if ((val & 3UL) == 2UL)
+			set_cpu_cap(c, X86_FEATURE_PPIN);

You may have copied a bug of mine from upstream. We recently found
a system where the BIOS enabled PPIN and set the lock bit.

If that is possible on AMD, then you should just check for enabled at this
point. "if (val & 2UL)"

See this commit in TIP tree:

59b5809655bd ("x86/mce: Fix logic and comments around MSR_PPIN_CTL")

Otherwise looks fine:

Acked-by: Tony Luck <tony.luck@...el.com>

-Tony

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