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Message-ID: <20200312200738.GB5086@worktop.programming.kicks-ass.net>
Date: Thu, 12 Mar 2020 21:07:38 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Josh Poimboeuf <jpoimboe@...hat.com>
Cc: Andy Lutomirski <luto@...capital.net>, x86@...nel.org,
linux-kernel@...r.kernel.org,
Vince Weaver <vincent.weaver@...ne.edu>,
Dave Jones <dsj@...com>, Jann Horn <jannh@...gle.com>,
Miroslav Benes <mbenes@...e.cz>,
Andy Lutomirski <luto@...nel.org>,
Steven Rostedt <rostedt@...dmis.org>,
Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH 03/14] x86/entry/64: Fix unwind hints in register
clearing code
On Thu, Mar 12, 2020 at 02:57:14PM -0500, Josh Poimboeuf wrote:
> On Thu, Mar 12, 2020 at 12:29:29PM -0700, Andy Lutomirski wrote:
> > > On Mar 12, 2020, at 10:31 AM, Josh Poimboeuf <jpoimboe@...hat.com> wrote:
> > >
> > > The PUSH_AND_CLEAR_REGS macro zeroes each register immediately after
> > > pushing it. If an NMI or exception hits after a register is cleared,
> > > but before the UNWIND_HINT_REGS annotation, the ORC unwinder will
> > > wrongly think the previous value of the register was zero. This can
> > > confuse the unwinding process and cause it to exit early.
> > >
> > > Because ORC is simpler than DWARF, there are a limited number of unwind
> > > annotation states, so it's not possible to add an individual unwind hint
> > > after each push/clear combination. Instead, the register clearing
> > > instructions need to be consolidated and moved to after the
> > > UNWIND_HINT_REGS annotation.
> >
> > I don’t suppose you know how bad t he performance hit is on a non-PTI machine?
>
> Hm, what does it have to do with PTI? Should I run a syscall
> microbenchmark?
Mostly that performance with PTI on is abysmal so we don't care about a
few cycles.
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