Message-ID: <CAL_JsqKRk+adXnej_XUU3dr9Z9G09oZTY+X1i=gYpD7vrbWCZg@mail.gmail.com>
Date:   Thu, 12 Mar 2020 08:47:56 -0500
From:   Rob Herring <robh+dt@...nel.org>
To:     Sergey.Semin@...kalelectronics.ru
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Mark Rutland <mark.rutland@....com>,
        Hoan Tran <hoan@...amperecomputing.com>,
        Serge Semin <fancer.lancer@...il.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        devicetree@...r.kernel.org,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/4] dt-bindings: gpio: Replace DW APB GPIO legacy
 bindings with YAML-based one

On Fri, Mar 6, 2020 at 7:25 AM <Sergey.Semin@...kalelectronics.ru> wrote:
>

Subject is kind of long and wordy. Perhaps:

dt-bindings: gpio: Convert snps,dw-apb-gpio to DT schema

> From: Serge Semin <Sergey.Semin@...kalelectronics.ru>
>
> Modern device tree bindings are supposed to be created as YAML-files
> in accordance with dt-schema. This commit replaces Synopsys DW GPIO
> legacy bare text bindings with YAML file. As before the bindings file
> states that the corresponding dts node is supposed to be compatible
> with generic DW I2C controller indicated by the "snps,dw-apb-gpio"
> compatible string and provide a mandatory registers memory range.
> It may also have an optional clocks and resets phandle references.
>
> There must be specified at least one subnode with
> "snps,dw-apb-gpio-port" compatible string indicating the GPIO port,
> which would actually export the GPIO controller functionality. Such
> nodes should have traditional GPIO controller properties together
> with optional interrupt-controller attributes if the corresponding
> controller was synthesized to detected and report the input values
> change to the parental IRQ controller.
>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
> Signed-off-by: Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
> Cc: Paul Burton <paulburton@...nel.org>
> Cc: Ralf Baechle <ralf@...ux-mips.org>
>
> ---
>
> Synopsis DesignWare APB SSI controller has a bindings property
> "snps,nr-gpios" of numeric type, which means the number of GPIO pins
> exported by the corresponding controller port. There is also a generic
> pattern-property "*-gpios", which corresponds to a GPIOs array. As you
> can see the GPIOs array property wildcard matches the vendor-specific
> property "snps,nr-gpios" property while having an incompatible type.
> Due to this the DW APB GPIO dts-nodes evaluation will report the
> following error:
>
> snps,nr-gpios:0:0: 8 is not valid under any of the given schemas (Possible causes of the failure):
> snps,nr-gpios:0:0: missing phandle tag in 8
>
> I didn't manage to fix the problem by redefining the property schema (this
> might be impossible anyway). In my opinion the best way to solve it would be
> to change the DW APB SSI Controller bindings so the driver would accept the
> standard "ngpios" property for the same purpose. But in this case we would have
> to alter all the dts files currently having the "snps,dw-apb-ssi" compatible
> nodes (it's a lot). I know the bindings modifications aren't that much welcome
> in the kernel community and there are good reasons why. So what do you think
> would be the better way to fix the problem with the property types collision?

Does this change (to dt-schema) work for you?

diff --git a/schemas/gpio/gpio.yaml b/schemas/gpio/gpio.yaml
index 1d9c109f9791..d1c08ccfdc1a 100644
--- a/schemas/gpio/gpio.yaml
+++ b/schemas/gpio/gpio.yaml
@@ -34,7 +34,7 @@ properties:
       - $ref: "/schemas/types.yaml#/definitions/phandle-array"

 patternProperties:
-  ".*-gpios?$":
+  "(?<!,nr)-gpios?$":
     $ref: "/schemas/types.yaml#/definitions/phandle-array"
   "^gpios$":
     $ref: "/schemas/types.yaml#/definitions/phandle-array"


> ---
>  .../bindings/gpio/snps,dw-apb-gpio.yaml       | 136 ++++++++++++++++++
>  .../bindings/gpio/snps-dwapb-gpio.txt         |  65 ---------
>  2 files changed, 136 insertions(+), 65 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
>  delete mode 100644 Documentation/devicetree/bindings/gpio/snps-dwapb-gpio.txt
>
> diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
> new file mode 100644
> index 000000000000..d9bc12e9e515
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
> @@ -0,0 +1,136 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

Do you have rights to add BSD?

> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys DesignWare APB GPIO controller
> +
> +description: |
> +  Synopsys DesignWare GPIO controllers have a configurable number of ports,
> +  each of which are intended to be represented as child nodes with the generic
> +  GPIO-controller properties as desribed in this bindings file.
> +
> +maintainers:
> +  - Hoan Tran <hoan@...amperecomputing.com>
> +
> +properties:
> +  $nodename:
> +    pattern: "^gpio@[0-9a-fA-F]+$"

Lowercase hex for unit-addresses.

> +
> +  compatible:
> +    const: snps,dw-apb-gpio
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: APB interface clock source
> +
> +  clock-names:
> +    items:
> +      - const: bus
> +
> +  resets:
> +    maxItems: 1
> +
> +patternProperties:
> +  "^.*@[0-9a-fA-F]+$":

Shouldn't it be "^gpio@..." And unit-addresses should be lowercase.

> +    type: object
> +    properties:
> +      compatible:
> +        const: snps,dw-apb-gpio-port
> +
> +      reg:
> +        maxItems: 1
> +
> +      gpio-controller: true
> +
> +      '#gpio-cells':
> +        const: 2
> +
> +      snps,nr-gpios:
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        description: The number of GPIO pins exported by the port.
> +        default: 32
> +        minimum: 1
> +        maximum: 32
> +
> +      interrupts:
> +        description: |
> +          The interrupts to the parent controller raised when GPIOs generate
> +          the interrupts. If the controller provides one combined interrupt
> +          for all GPIOs, specify a single interrupt. If the controller provides
> +          one interrupt for each GPIO, provide a list of interrupts that
> +          correspond to each of the GPIO pins.
> +        minItems: 1
> +        maxItems: 32
> +
> +      interrupts-extended:

Drop this. It gets added by the tools automatically.

> +        description: |
> +          When specifying multiple interrupts, if any are unconnected, use
> +          this property to specify the interrupts and set the interrupt
> +          controller handle for unused interrupts to 0.
> +        minItems: 1
> +        maxItems: 32
> +
> +      interrupt-controller: true
> +
> +      '#interrupt-cells':
> +        const: 2
> +
> +    required:
> +      - compatible
> +      - reg
> +      - gpio-controller
> +      - '#gpio-cells'
> +
> +    dependencies:
> +      interrupt-controller: [ interrupts ]
> +
> +    additionalProperties: false
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#address-cells"
> +  - "#size-cells"
> +
> +examples:
> +  - |
> +    gpio: gpio@...00 {
> +      compatible = "snps,dw-apb-gpio";
> +      reg = <0x20000 0x1000>;
> +      #address-cells = <1>;
> +      #size-cells = <0>;
> +
> +      porta: gpio@0 {
> +        compatible = "snps,dw-apb-gpio-port";
> +        reg = <0>;
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        snps,nr-gpios = <8>;
> +        interrupt-controller;
> +        #interrupt-cells = <2>;
> +        interrupt-parent = <&vic1>;
> +        interrupts = <0>;
> +      };
> +
> +      portb: gpio@1 {
> +        compatible = "snps,dw-apb-gpio-port";
> +        reg = <1>;
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        snps,nr-gpios = <8>;
> +      };
> +    };
> +...

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