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Message-ID: <1584092066-24425-3-git-send-email-henryc.chen@mediatek.com>
Date: Fri, 13 Mar 2020 17:34:15 +0800
From: Henry Chen <henryc.chen@...iatek.com>
To: Georgi Djakov <georgi.djakov@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Viresh Kumar <vireshk@...nel.org>,
Stephen Boyd <swboyd@...omium.org>,
Ryan Case <ryandcase@...omium.org>,
Mark Brown <broonie@...nel.org>
CC: Mark Rutland <mark.rutland@....com>,
Nicolas Boichat <drinkcat@...gle.com>,
Fan Chen <fan.chen@...iatek.com>,
James Liao <jamesjj.liao@...iatek.com>,
Arvin Wang <arvin.wang@...iatek.com>,
Mike Turquette <mturquette@...aro.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org>,
<srv_heupstream@...iatek.com>,
Henry Chen <henryc.chen@...iatek.com>
Subject: [PATCH V4 02/13] dt-bindings: soc: Add opp table on scpsys bindings
Add opp table on scpsys dt-bindings for Mediatek SoC.
Signed-off-by: Henry Chen <henryc.chen@...iatek.com>
Reviewed-by: Rob Herring <robh@...nel.org>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 1baaa6f..d22f11d 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -70,6 +70,10 @@ Optional properties:
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
+- operating-points-v2: Phandle to the OPP table for the Power domain.
+ Refer to Documentation/devicetree/bindings/power/power_domain.txt
+ and Documentation/devicetree/bindings/opp/opp.txt for more details
+
Example:
scpsys: scpsys@...06000 {
@@ -82,6 +86,27 @@ Example:
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
+ operating-points-v2 = <&dvfsrc_opp_table>;
+
+ dvfsrc_opp_table: opp-table {
+ compatible = "operating-points-v2-level";
+
+ dvfsrc_vol_min: opp1 {
+ opp,level = <MT8183_DVFSRC_LEVEL_1>;
+ };
+
+ dvfsrc_freq_medium: opp2 {
+ opp,level = <MT8183_DVFSRC_LEVEL_2>;
+ };
+
+ dvfsrc_freq_max: opp3 {
+ opp,level = <MT8183_DVFSRC_LEVEL_3>;
+ };
+
+ dvfsrc_vol_max: opp4 {
+ opp,level = <MT8183_DVFSRC_LEVEL_4>;
+ };
+ };
};
Example consumer:
@@ -89,4 +114,21 @@ Example consumer:
afe: mt8173-afe-pcm@...20000 {
compatible = "mediatek,mt8173-afe-pcm";
power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+ operating-points-v2 = <&aud_opp_table>;
+ };
+
+ aud_opp_table: aud-opp-table {
+ compatible = "operating-points-v2";
+ opp1 {
+ opp-hz = /bits/ 64 <793000000>;
+ required-opps = <&dvfsrc_vol_min>;
+ };
+ opp2 {
+ opp-hz = /bits/ 64 <910000000>;
+ required-opps = <&dvfsrc_vol_max>;
+ };
+ opp3 {
+ opp-hz = /bits/ 64 <1014000000>;
+ required-opps = <&dvfsrc_vol_max>;
+ };
};
--
1.9.1
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