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Message-Id: <20200314133600.183-1-ansuelsmth@gmail.com>
Date: Sat, 14 Mar 2020 14:36:00 +0100
From: Ansuel Smith <ansuelsmth@...il.com>
To: agross@...nel.org
Cc: Ansuel Smith <ansuelsmth@...il.com>,
Abhishek Sahu <absahu@...eaurora.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Kumar Gala <galak@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [RESEND PATCH] ipq806x: gcc: Added the enable regs and mask for PRNG
Kernel got hanged while reading from /dev/hwrng at the
time of PRNG clock enable
Fixes: 24d8fba44af3 "clk: qcom: Add support for IPQ8064's global
clock controller (GCC)"
Signed-off-by: Abhishek Sahu <absahu@...eaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index b0eee0903807..a8456e09c44d 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -1224,6 +1224,8 @@ static struct clk_rcg prng_src = {
.parent_map = gcc_pxo_pll8_map,
},
.clkr = {
+ .enable_reg = 0x2e80,
+ .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_names = gcc_pxo_pll8,
--
2.25.0
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