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Date: Sat, 14 Mar 2020 18:46:02 -0700 From: Sowjanya Komatineni <skomatineni@...dia.com> To: <skomatineni@...dia.com>, <thierry.reding@...il.com>, <jonathanh@...dia.com>, <frankc@...dia.com>, <hverkuil@...all.nl>, <helen.koike@...labora.com>, <sboyd@...nel.org> CC: <linux-media@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-clk@...r.kernel.org>, <linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org> Subject: [RFC PATCH v4 4/8] clk: tegra: Add Tegra210 CSI TPG clock gate Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd <sboyd@...nel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com> --- drivers/clk/tegra/clk-tegra210.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index c6304f5..58a67c7 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -3035,6 +3035,13 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, periph_clk_enb_refcnt); clks[TEGRA210_CLK_DSIB] = clk; + /* csi_tpg */ + clk = clk_register_gate(NULL, "csi_tpg", "pll_d_out0", + CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, + 23, 0, &pll_d_lock); + clk_register_clkdev(clk, "csi_tpg", NULL); + clks[TEGRA210_CLK_CSI_TPG] = clk; + /* la */ clk = tegra_clk_register_periph("la", la_parents, ARRAY_SIZE(la_parents), &tegra210_la, clk_base, -- 2.7.4
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