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Message-Id: <1584356082-26769-3-git-send-email-tdas@codeaurora.org>
Date: Mon, 16 Mar 2020 16:24:41 +0530
From: Taniya Das <tdas@...eaurora.org>
To: Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>
Cc: David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Andy Gross <agross@...nel.org>, devicetree@...r.kernel.org,
robh@...nel.org, robh+dt@...nel.org,
Taniya Das <tdas@...eaurora.org>
Subject: [PATCH v1 2/3] dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
The gcc_sec_ctrl_clk_src clock is required to be controlled by the
secure controller driver.
Signed-off-by: Taniya Das <tdas@...eaurora.org>
---
include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h
index e8029b2e..281d0b4 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc7180.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h
@@ -132,6 +132,7 @@
#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122
#define GCC_VIDEO_THROTTLE_AXI_CLK 123
#define GCC_VIDEO_XO_CLK 124
+#define GCC_SEC_CTRL_CLK_SRC 125
/* GCC resets */
#define GCC_QUSB2PHY_PRIM_BCR 0
--
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