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Message-ID: <20200316154023.GA8550@e121166-lin.cambridge.arm.com>
Date: Mon, 16 Mar 2020 15:40:23 +0000
From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To: Kishon Vijay Abraham I <kishon@...com>
Cc: Murali Karicheri <m-karicheri2@...com>,
Andrew Murray <amurray@...goodpenguin.co.uk>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, Xiaowei Bao <xiaowei.bao@....com>
Subject: Re: [PATCH v2 0/3] PCIe: Endpoint: Redesign MSI-X support
On Tue, Feb 25, 2020 at 01:47:00PM +0530, Kishon Vijay Abraham I wrote:
> Existing MSI-X support in Endpoint core has limitations:
> 1) MSIX table (which is mapped to a BAR) is not allocated by
> anyone. Ideally this should be allocated by endpoint
> function driver.
> 2) Endpoint controller can choose any random BARs for MSIX
> table (irrespective of whether the endpoint function driver
> has allocated memory for it or not)
>
> In order to avoid these limitations, pci_epc_set_msix() is
> modified to include BAR Indicator register (BIR) configuration
> and MSIX table offset as arguments. This series also fixed MSIX
> support in dwc driver and add MSI-X support in Cadence PCIe driver.
>
> Changes from v1:
> *) Removed Cadence MSI-X support from the series
> *) Fixed nits pointed out by Bjorn
>
> Kishon Vijay Abraham I (3):
> PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
> PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table
> address
> PCI: keystone: Allow AM654 PCIe Endpoint to raise MSI-X interrupt
>
> drivers/pci/controller/dwc/pci-keystone.c | 5 +-
> .../pci/controller/dwc/pcie-designware-ep.c | 61 +++++++++----------
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> drivers/pci/endpoint/functions/pci-epf-test.c | 31 ++++++++--
> drivers/pci/endpoint/pci-epc-core.c | 7 ++-
> drivers/pci/endpoint/pci-epf-core.c | 2 +
> include/linux/pci-epc.h | 6 +-
> include/linux/pci-epf.h | 15 +++++
> 8 files changed, 86 insertions(+), 42 deletions(-)
I have applied it to pci/endpoint for v5.7, thanks.
Lorenzo
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