linux-kernel - Re: [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <158437819409.88485.6326749791923076608@swboyd.mtv.corp.google.com>
Date:   Mon, 16 Mar 2020 10:03:14 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Wesley Cheng <wcheng@...eaurora.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, mark.rutland@....com,
        mturquette@...libre.com, robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Wesley Cheng <wcheng@...eaurora.org>
Subject: Re: [PATCH 2/3] clk: qcom: gcc: Add USB3 PIPE clock operations

Quoting Wesley Cheng (2020-03-14 00:51:58)
> Add the USB3 PIPE clock structures, so that the USB driver can
> vote for the GCC to enable/disable it when required.  This clock
> is needed for SSUSB operation.
> 
> Signed-off-by: Wesley Cheng <wcheng@...eaurora.org>
> ---
>  drivers/clk/qcom/gcc-sm8150.c | 26 ++++++++++++++++++++++++++

Can you please combine these two patches and add sm8150 in the subject?

>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index d0cd03d..ef98fdc 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -3172,6 +3172,18 @@ enum {
>         },
>  };
>  
> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
> +       .halt_check = BRANCH_HALT_SKIP,
> +       .clkr = {
> +               .enable_reg = 0xf058,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_usb3_prim_phy_pipe_clk",
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_branch gcc_usb3_sec_clkref_clk = {
>         .halt_reg = 0x8c028,
>         .halt_check = BRANCH_HALT,
> @@ -3219,6 +3231,18 @@ enum {
>         },
>  };
>  
> +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
> +       .halt_check = BRANCH_HALT_SKIP,

Sad to see that we'll never resolve this.