linux-kernel - Re: [PATCH v2 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150

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Message-ID: <158474728076.125146.11401827374115414324@swboyd.mtv.corp.google.com>
Date:   Fri, 20 Mar 2020 16:34:40 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Wesley Cheng <wcheng@...eaurora.org>, agross@...nel.org,
        bjorn.andersson@...aro.org, mark.rutland@....com,
        mturquette@...libre.com, robh+dt@...nel.org
Cc:     linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Wesley Cheng <wcheng@...eaurora.org>
Subject: Re: [PATCH v2 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150

Quoting Wesley Cheng (2020-03-17 13:53:31)
> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
> index 90d60ef..3e1a918 100644
> --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
> +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
> @@ -240,4 +240,8 @@
>  #define GCC_USB30_SEC_BCR                                      27
>  #define GCC_USB_PHY_CFG_AHB2PHY_BCR                            28
>  
> +/* GCC GDSCRs */
> +#define USB30_PRIM_GDSC                     4
> +#define USB30_SEC_GDSC                                         5

BTW, should we expect more GDSCs at 0,1,2,3 here? Why wasn't that done
initially?