linux-kernel - Re: [PATCH] arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes

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Message-ID: <3dcb6199-2276-7aa5-2857-1208f8024b56@ti.com>
Date:   Fri, 20 Mar 2020 11:07:00 +0200
From:   Tero Kristo <t-kristo@...com>
To:     Roger Quadros <rogerq@...com>
CC:     <nm@...com>, <d-gerlach@...com>, <nsekhar@...com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <stable@...nel.org>
Subject: Re: [PATCH] arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes

On 11/03/2020 16:41, Roger Quadros wrote:
> From: Dave Gerlach <d-gerlach@...com>
> 
> The TI sci-clk driver can scan the DT for all clocks provided by system
> firmware and does this by checking the clocks property of all nodes, so
> we must add this to the dwc3 nodes so USB clocks are available.
> 
> Without this USB does not work with latest system firmware i.e.
> [    1.714662] clk: couldn't get parent clock 0 for /interconnect@...000/dwc3@...0000
> 
> Fixes: cc54a99464ccd ("arm64: dts: ti: k3-am6: add USB suppor")
> Signed-off-by: Dave Gerlach <d-gerlach@...com>
> Signed-off-by: Roger Quadros <rogerq@...com>
> Cc: stable@...nel.org
> ---

Queued up towards 5.7, thanks.

-Tero

>   arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index e5df20a2d2f9..d86c5c7b82fc 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -296,6 +296,7 @@
>   		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
>   		dma-coherent;
>   		power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
>   		assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
>   		assigned-clock-parents = <&k3_clks 151 4>,	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
>   					 <&k3_clks 151 9>;	/* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
> @@ -335,6 +336,7 @@
>   		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
>   		dma-coherent;
>   		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
> +		clocks = <&k3_clks 152 2>;
>   		assigned-clocks = <&k3_clks 152 2>;
>   		assigned-clock-parents = <&k3_clks 152 4>;	/* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
>   
> 

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