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Message-Id: <20200320133452.3705040-5-thierry.reding@gmail.com>
Date: Fri, 20 Mar 2020 14:34:49 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Thomas Gleixner <tglx@...utronix.de>,
Thierry Reding <thierry.reding@...il.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Jon Hunter <jonathanh@...dia.com>, linux-tegra@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 4/7] arm64: tegra: Add native timer support on Tegra186
From: Thierry Reding <treding@...dia.com>
The native timers IP block found on NVIDIA Tegra SoCs implements a
watchdog timer that can be used to recover from system hangs. Add the
device tree node on Tegra186.
Signed-off-by: Thierry Reding <treding@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 58100fb9cd8b..4dfa70e93693 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -167,6 +167,22 @@ emc: external-memory-controller@...0000 {
};
};
+ timer@...0000 {
+ compatible = "nvidia,tegra186-timer";
+ reg = <0x0 0x03010000 0x0 0x000e0000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
uarta: serial@...0000 {
compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
reg = <0x0 0x03100000 0x0 0x40>;
--
2.24.1
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