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Message-Id: <20200320174107.29406-4-lkundrak@v3.sk>
Date: Fri, 20 Mar 2020 18:41:00 +0100
From: Lubomir Rintel <lkundrak@...sk>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Daniel Mack <daniel@...que.org>,
Haojian Zhuang <haojian.zhuang@...il.com>,
Robert Jarzmik <robert.jarzmik@...e.fr>,
Marc Gonzalez <marc.w.gonzalez@...e.fr>,
Mans Rullgard <mans@...sr.com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Paul Mackerras <paulus@...ba.org>,
Michael Ellerman <mpe@...erman.id.au>,
linuxppc-dev@...ts.ozlabs.org, linux-serial@...r.kernel.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Lubomir Rintel <lkundrak@...sk>
Subject: [PATCH 03/10] ARM: dts: pxa*: Make the serial ports compatible with xscale-uart
Some drivers that claim to support mrvl,mmp-uart default to a reg-shift
of two, some don't. Be explicit to be on a safe side.
With that in place, a XScale serial port driver is perfectly capable of
supporting the MMP serial port. Add a compatible string.
Signed-off-by: Lubomir Rintel <lkundrak@...sk>
---
arch/arm/boot/dts/pxa168.dtsi | 9 ++++++---
arch/arm/boot/dts/pxa910.dtsi | 9 ++++++---
2 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi
index 41dc79c9f6320..9a9e38245e88c 100644
--- a/arch/arm/boot/dts/pxa168.dtsi
+++ b/arch/arm/boot/dts/pxa168.dtsi
@@ -56,8 +56,9 @@ timer0: timer@...14000 {
};
uart1: serial@...17000 {
- compatible = "mrvl,mmp-uart";
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4017000 0x1000>;
+ reg-shift = <2>;
interrupts = <27>;
clocks = <&soc_clocks PXA168_CLK_UART0>;
resets = <&soc_clocks PXA168_CLK_UART0>;
@@ -65,8 +66,9 @@ uart1: serial@...17000 {
};
uart2: serial@...18000 {
- compatible = "mrvl,mmp-uart";
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4018000 0x1000>;
+ reg-shift = <2>;
interrupts = <28>;
clocks = <&soc_clocks PXA168_CLK_UART1>;
resets = <&soc_clocks PXA168_CLK_UART1>;
@@ -74,8 +76,9 @@ uart2: serial@...18000 {
};
uart3: serial@...26000 {
- compatible = "mrvl,mmp-uart";
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4026000 0x1000>;
+ reg-shift = <2>;
interrupts = <29>;
clocks = <&soc_clocks PXA168_CLK_UART2>;
resets = <&soc_clocks PXA168_CLK_UART2>;
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index 209b1f0ea67b2..587a5e7f0702f 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -68,8 +68,9 @@ timer1: timer@...16000 {
};
uart1: serial@...17000 {
- compatible = "mrvl,mmp-uart";
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4017000 0x1000>;
+ reg-shift = <2>;
interrupts = <27>;
clocks = <&soc_clocks PXA910_CLK_UART0>;
resets = <&soc_clocks PXA910_CLK_UART0>;
@@ -77,8 +78,9 @@ uart1: serial@...17000 {
};
uart2: serial@...18000 {
- compatible = "mrvl,mmp-uart";
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4018000 0x1000>;
+ reg-shift = <2>;
interrupts = <28>;
clocks = <&soc_clocks PXA910_CLK_UART1>;
resets = <&soc_clocks PXA910_CLK_UART1>;
@@ -86,8 +88,9 @@ uart2: serial@...18000 {
};
uart3: serial@...36000 {
- compatible = "mrvl,mmp-uart";
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
reg = <0xd4036000 0x1000>;
+ reg-shift = <2>;
interrupts = <59>;
clocks = <&soc_clocks PXA910_CLK_UART2>;
resets = <&soc_clocks PXA910_CLK_UART2>;
--
2.25.1
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