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Message-ID: <40704a28b562167b58992c036bff4f81@kernel.org>
Date:   Sat, 21 Mar 2020 09:54:31 +0000
From:   Marc Zyngier <maz@...nel.org>
To:     Heyi Guo <guoheyi@...wei.com>
Cc:     linux-kernel@...r.kernel.org, wanghaibin.wang@...wei.com,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>
Subject: Re: [PATCH] irq/gic-its: gicv4: set VPENDING table as inner-shareable

Hi Heyi,

On 2020-02-24 02:22, Heyi Guo wrote:
> Hi Marc,
> 
> On 2019/12/2 2:04, Marc Zyngier wrote:
>> On Sat, 30 Nov 2019 15:38:49 +0800
>> Heyi Guo <guoheyi@...wei.com> wrote:
>> 
>>> There is no special reason to set virtual LPI pending table as
>>> non-shareable. If we choose to hard code the shareability without
>>> probing, inner-shareable will be a better choice, for all the other
>>> ITS/GICR tables prefer to be inner-shareable.
>> One of the issues is that we have strictly no idea what the caches are
>> Inner Shareable with (I've been asking for such clarification for 
>> years
>> without getting anywhere). You can have as many disconnected inner
>> shareable domains as you want!
>> 
>> I suspect that in the grand scheme of things, the redistributors
>> ought to be in the same inner shareable domain, and that with a bit of
>> luck, the CPUs are there as well. Still, that's a massive guess.
>> 
>>> What's more, on Hisilicon hip08 it will trigger some kind of bus
>>> warning when mixing use of different shareabilities.
>> Do you have more information about what the bus is complaining about?
>> Is that because the CPUs have these pages mapped as inner shareable?
>> 
>> I'll give it a go on D05 (HIP07) to find out what changes there.
> 
> How's your go on D05? Did you see any issues?

Sorry it took so long. I've given it a go on my D05, and didn't notice
anything bad (or rather, nothing worse than usual, since GICv4 on this
machine is pretty... funky).

I've now take this into the 5.7 queue.

Thanks,

          M.
-- 
Jazz is not dead. It just smells funny...

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