linux-kernel - [PATCH v2 2/2] dt-bindings: remoteproc: Add documentation for SPSS remoteproc

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 20 Mar 2020 18:32:10 -0700
From:   Rishabh Bhatnagar <rishabhb@...eaurora.org>
To:     linux-remoteproc-owner@...r.kernel.org,
        linux-kernel@...r.kernel.org, bjorn.andersson@...aro.org,
        mathieu.poirier@...aro.org, devicetree@...r.kernel.org
Cc:     robh@...nel.org, psodagud@...eaurora.org, tsoni@...eaurora.org,
        sidgup@...eaurora.org, Rishabh Bhatnagar <rishabhb@...eaurora.org>
Subject: [PATCH v2 2/2] dt-bindings: remoteproc: Add documentation for SPSS remoteproc

Add devicetree binding for Secure Subsystem remote processor
support in remoteproc framework. This describes all the resources
needed by SPSS to boot and handle crash and shutdown scenarios.

Signed-off-by: Rishabh Bhatnagar <rishabhb@...eaurora.org>
---
 .../devicetree/bindings/remoteproc/qcom,spss.yaml  | 125 +++++++++++++++++++++
 1 file changed, 125 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,spss.yaml

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,spss.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,spss.yaml
new file mode 100644
index 0000000..9ca7947a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,spss.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/qcom,spss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SPSS Peripheral Image Loader
+
+maintainers:
+  - Rishabh Bhatnagar <rishabhb@...eaurora.org>
+description: |
+  This document defines the binding for a component that loads and boots firmware
+  on the Qualcomm Secure Peripheral Processor. This processor is booted in the
+  bootloader stage and it attaches itself to linux later on in the boot process.
+
+properties:
+  compatible:
+    enum:
+      "qcom,sm8250-spss-pas"
+
+  reg:
+    items:
+      - description: IRQ status register
+      - description: IRQ clear register
+      - description: IRQ mask register
+      - description: Error register
+      - description: Error spare register
+
+  reg-names:
+    items:
+      - const: sp2soc_irq_status
+      - const: sp2soc_irq_clr
+      - const: sp2soc_irq_mask
+      - const: rmb_err
+      - const: rmb_err_spare2
+
+  interrupts:
+    maxitems: 1
+    items:
+      - description: rx interrupt
+
+  clocks:
+    items:
+      - description:
+                    reference to the xo clock to be held on behalf
+                    of the booting Hexagon core
+
+  clock-names:
+    items:
+      - const: xo
+
+  cx-supply: true
+
+  px-supply: true
+
+  memory-region: true
+    items:
+      - description: reference to the reserved-memory for the SPSS
+
+  qcom,spss-scsr-bits:
+    - description: Bits that are set by remote processor in the irq status
+                   register region to represent different states during
+                   boot process
+
+  child-node:
+    description: Subnode named either "smd-edge" or "glink-edge" that
+                 describes the communication edge, channels and devices
+                 related to the SPSS.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - clocks
+  - clock-names
+  - cx-supply
+  - px-supply
+  - memory-region
+  - qcom,spss-scsr-bits
+
+
+examples:
+  - |
+    spss {
+        compatible = "qcom,sm8250-spss-pil";
+        reg = <0x188101c 0x4>,
+                <0x1881024 0x4>,
+                <0x1881028 0x4>,
+                <0x188103c 0x4>,
+                <0x1882014 0x4>;
+        reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
+                    "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
+        interrupts = <0 352 1>;
+
+        cx-supply = <&VDD_CX_LEVEL>;
+        cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+        px-supply = <&VDD_MX_LEVEL>;
+        px-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+        clocks = <&clock_rpmh RPMH_CXO_CLK>;
+        clock-names = "xo";
+        qcom,proxy-clock-names = "xo";
+        status = "ok";
+
+        memory-region = <&pil_spss_mem>;
+        qcom,spss-scsr-bits = <24 25>;
+
+        glink-edge {
+                qcom,remote-pid = <8>;
+                transport = "spss";
+                mboxes = <&sp_scsr 0>;
+                mbox-names = "spss_spss";
+                interrupt-parent = <&intsp>;
+                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+
+                reg = <0x1885008 0x8>,
+                      <0x1885010 0x4>;
+                reg-names = "qcom,spss-addr",
+                            "qcom,spss-size";
+
+                label = "spss";
+                qcom,glink-label = "spss";
+        };
+    };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project